Jos Dreesen <jos.mar at bluewin.ch> wrote: I'm well aware of Alliance and it's awesome, but it's for ASICs rather than FPGAs. The interesting question is whether the P&R function from Alliance could be ported to an FPGA. Suppose we found an FPGA for which we have a complete definition of the routing fabric and configuration image format, or obtained this information for some common commercial FPGA through someone with the right connections or through reverse engineering. We would still need a P&R tool, which is a very major task. I wonder if the P&R function from Alliance could be adapted to the task. But I don't know any of the fundamental theory behind P&R in ASICs versus FPGAs to know whether this could be done or if it's a totally different problem. Now if we only had the bucks to fab a real chip instead of screwing with FPGAs... Then we could use Alliance and go completely open source from start to finish. Does anyone know how much does it cost to fab a chip? MS