UNIBUS <-> PCI bridge - test-drb@ccmp.vtda.org

9 Aug 2009

Roger Ivie <rivie at ridgenet.net> wrote:

...
  On Fri, 7 Aug 2009, Johnny Billquist wrote:
  > Interrupt stuff is usually a bit more
complicated than what you seem to 
 > envision above. You have the interrupt request line, the interrupt grants, 
 > which is followed by the vector at the interrupt acknowledge, and then you 
 > have the interrupt dismiss stuff, which cause the device to remove the 
 > interrupt request, and allow other devices at the same priority, but farther 
 > from the bus arbiter to get their interrupt through.  
 Interrupts are actually a bit odd on the UNIBUS, where interrupt
 requests are really just prioritized DMA requests. A UNIBUS device
 asserts a bus request and gets a bus grant, at which point it may do
 *any* kind of bus traffic. Providing a vector to the computer is just a
 specialized kind of DMA write; one with an implied address, as it were. 
Hmm. Now I'm just writing from memory, which sometimes is a really big 
mistake, but I don't think that is correct.

First of all, interrupt bus requests are only granted at instruction 
fetch time, while DMA bus requests can be granted at any stage of the 
CPU execution cycle.
Second, the vector transfer isn't a normal bus transfer in the sense of 
the device addressing the CPU and transferring a word. The CPU cannot be 
a slave, unless my memory fails me. However, at the interrupt 
acknowledge cycle, the device is expected to put out the vector, and the 
CPU will read the data in from the bus and gate it into temporary 
storage, followed by pushing the PSW and PC, and reading a new PSW and 
PC from the address given by the vector.

This is a rather complex behaviour, and not something you can manage to 
trick the CPU into doing under any other circumstances.

As for asserting the interrupt request, and getting a bus grant in 
return, that is pretty much how all CPUs work. The big difference is 
only in what they call the signal, and how the device is expected to 
behave once the grant comes in.

Many CPUs have just a single interrupt request line, and a single 
interrupt acknowledge line. The fact that the Unibus defines four is 
nice, though. :-)

...
  It's been a few years, time kills brain cells,
yadda yadda yadda, but I
 did actually design a UNIBUS processor board once upon a time. With a 
 UNIBUS map. The PDP-11 UNIBUS map is not as simple as the one used on the 
 VAX. 
It's been way many years since I looked at the unibus map of the VAX 
UBA, but I can't for my life imagine that it could be any simpler than 
the Unibus map of the PDP-11.

But maybe that's just me. :-)

	Johnny

-- 
Johnny Billquist                  || "I'm on a bus
                                   ||  on a psychedelic trip
email: bqt at softjar.se             ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol