Appendix D in the 003 rev of the /24 TM has the details of the -YA.. Checking grant line continuity is part of system setup for me; the fact than on many backplanes, the DMA grant jumpering is wirewrap on the back of the backplane is a PITA, but back when it wasn't that big a deal. (Heck, configuration jumpering on boards was all soldered wires BITD!) The need for grant continuity is actually a characteristic of the _CPU_, not the bus. I was astonished the first time I played with an /04 (or naybe it was a /34, I forget), because on them, I'm pretty sure (I can't find it in the documentation, but I'm pretty sure I remember it) that on power-on, the CPU checks for grant continuity, and won't work without it. (They all require the M9302 teminator or equivalent, which has active circuitry to turn around an unclaimed grant onto the BSACK line.) When the CPU powers up, it sends grants down the grant lines and expects to see them back on SACK (from the M9302), and it won't operate if this doesn't happen. That floored me when I ran across it, because on the older UNIBUS CPUs I'd worked with BITD (/40's, etc) it was the done thing to be able to leave a gap in the grant _downtream_ of the last card that could do interrupts; no possible operational problem. I'm not sure why DEC added that 'feature'; probably somebody thought it would make systems more robust, but I bet all it did was generate a bunch of Field Circus calls. (Kind of like the LSI-11 'feature' where ODT won't start unless there's working memory at 0 - another wonderful little Easter Egg.) Ironically, although the QBUS uses _exactly_ the same kind of bus grant lines, no QBUS processor seems to check their continuity in this way; I habitually run my QBUS machines without all the slots filled, and F11 and J11 processors all run fine with open grant lines (after the last card that uses interrupts). I guess DEC found out the hard way that that check wasn't useful! But this, as I said, is a characteristic of the CPU, not the bus. QBUS documentation has long ediscussions of maximum cable lengths between backplane sections, but little about cases where termination on both ends is not needed. One exception is in the " pdp11 bus hanbook", pg. 128: If nore than 20 AC loads are included [on a single bacplane], the other end of the bus must be terminated with 120 ohms. The clear implication is that with <20 AC loads, termination at the second end is not needed. No explanation is given as to why, but I had the same thoughts as Patrick Finnegan - that it's down to the very short bus lengths. (With a short bus, the reflection from the un-terminated end will be very close in time - the line length for the lines on a single backplane is spec'd at a max od about 14"; so about 1 nsec. That's on the order of magnitude of the bus signal rise times.) If you think about it, every time you plug in a card, you've added a short branch to the bus on every bus line (since they aren't normally terminated at the transmitter/reveiver chips). But very short branches, so their reflections are even closer in time. Noel