26 Sep
2005
26 Sep
'05
11:09 p.m.
If a tristate buffer is enabled by its control line, but the input to
the buffer is at high-Z is there a typical output?
I checked the relevant datasheet, but this situation isn't covered.
There's timing for when the buffer is enabled and the input switches
from L to H or H to L, but nothing about the input at
high-Z.
The truth table as written in the datasheet:
2OE 2A 2Y
H H H
H L L
L X Z
I need another row for
2OE 2A 2Y
H Z ?
Where OE is the control, A is the input and Y is the output.
I'm still futzing about with this IIfx SIMM idea. I plan to use a
pair of SN74ABT241A octal buffers to make the 16M X 4 chips look as
if they have separate Din and Dout pins. And I planned to use the
WE_ signal as the control to the buffers.
However, it occurred to me that the computer might hold WE high at
all times except during writes. This would leave the Dout path
enabled almost all the time, which might interfere with other
activity on the data bus.
Once CAS goes high, the Dout of the DRAM chips would go back to
high-Z, so the computer designers would figure, leaving WE_ high most
times is fine. DRAM output is high-Z unless one just did a read with
a CAS signal.
But if I'm feeding the DRAM output into a tristate buffer this might
not work. The high-Z from the DRAM goes to the buffer as input. The
WE_ signal enables the buffer. What comes out the other end of the
tristate buffer onto the data bus? If the buffer drives the data bus
in this situation, then this won't work.
I really don't want to add an AND gate and an inverter so I can
change OE for the tristate buffer to WE*CAS'.
Of course, if WE_ is floating most of the time, it's not a problem.
I just lightly tie OE to GND and when WE floats, the buffer outputs
go to high-Z. But I can't count on that.
Run off a set with spaces for all the possible control signals I can
imagine and experiment?
Jeff Walther
27 Sep
27 Sep
12:47 p.m.
Most TTL (74xxx) series parts have pull up resistors on their inputs so they
will typically interpret a High-Z condition as a "1" or high input.
I'm not sure what you're trying to do with the separate Din/Dout
configuration. Are you trying to interface the 16Mx4 chip onto an existing
motherboard or memory card or design a new add in card? That info would
help with the advice.
Robo
----- Original Message -----
From: "Jeff Walther" <trag at io.com>
To: <cctech at classiccmp.org>
Sent: Monday, September 26, 2005 7:09 PM
Subject: Re: Tristate Buffer Output if Input is High-Z?
If a tristate buffer is enabled by its control line,
but the input to the
buffer is at high-Z is there a typical output?
I checked the relevant datasheet, but this situation isn't covered.
There's timing for when the buffer is enabled and the input switches from
L to H or H to L, but nothing about the input at high-Z.
The truth table as written in the datasheet:
2OE 2A 2Y
H H H
H L L
L X Z
I need another row for
2OE 2A 2Y
H Z ?
Where OE is the control, A is the input and Y is the output.
I'm still futzing about with this IIfx SIMM idea. I plan to use a pair
of SN74ABT241A octal buffers to make the 16M X 4 chips look as if they
have separate Din and Dout pins. And I planned to use the WE_ signal as
the control to the buffers.
However, it occurred to me that the computer might hold WE high at all
times except during writes. This would leave the Dout path enabled almost
all the time, which might interfere with other activity on the data bus.
Once CAS goes high, the Dout of the DRAM chips would go back to high-Z, so
the computer designers would figure, leaving WE_ high most times is fine.
DRAM output is high-Z unless one just did a read with a CAS signal.
But if I'm feeding the DRAM output into a tristate buffer this might not
work. The high-Z from the DRAM goes to the buffer as input. The WE_
signal enables the buffer. What comes out the other end of the tristate
buffer onto the data bus? If the buffer drives the data bus in this
situation, then this won't work.
I really don't want to add an AND gate and an inverter so I can change OE
for the tristate buffer to WE*CAS'.
Of course, if WE_ is floating most of the time, it's not a problem. I just
lightly tie OE to GND and when WE floats, the buffer outputs go to high-Z.
But I can't count on that.
Run off a set with spaces for all the possible control signals I can
imagine and experiment?
Jeff Walther
2:53 p.m.
>>>> "Jeff" == Jeff Walther
<trag at io.com> writes:
Jeff> If a tristate buffer is enabled by its control line, but the
Jeff> input to the buffer is at high-Z is there a typical output?
Not necessarily.
Hi-Z means the source of your input is not driving it. That means it
is equivalent to an unconnected input. Does your device have an
internal pull-up or pull-down? If yes, then an unconnected input is
equivalent to a high input, or low input, respectively.
If it doesn't have a pull-up or pull-down, then you have a floating
input, which means the behavior is undefined. It may be bouncing on
and off due to noise; it may end up behaving like low in one chip and
high in another of the same type, based on process variations; it may
change from one to the other as temperature changes. Oh yes, and if
it's CMOS it will probably draw more current than you expect because
you're not driving it to a well defined high or low state.
You should always have a defined input signal for all inputs. That
can be an internal pull-up/down; it can be an external one; or it can
be that you arrange for it always to be explicitly driven (always
exactly one source *not* in high-Z mode).
paul
4:14 p.m.
--- Jeff Walther <trag at io.com> wrote:
If a tristate buffer is enabled by its control line,
but the input to
the buffer is at high-Z is there a typical output?
High, but with less noise immunity then if you tied
the input high. The immunity could vary with the TTL
family, but leaving unused inputs floating was
standard practice with "standard" TTL, for instance.
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4:35 p.m.
If a tristate
buffer is enabled by its control line, but the input
to the buffer is at high-Z is there a typical output?
High, but with less noise
immunity then if you tied the input high.
The immunity could vary with the TTL family, but leaving unused
inputs floating was standard practice with "standard" TTL, for
instance. 
4:49 p.m.
On 9/26/2005 at 6:09 PM Jeff Walther wrote:
If a tristate buffer is enabled by its control line,
but the input to
the buffer is at high-Z is there a typical output?
I think I understand what you're asking, but I'm not sure.
If it's straight bipolar TTL, the high-Z input is usually at a "high" level.
But iwith CMOS, you're in terra incognita. Stray charges can linger on lines a lot
longer than on bipolar. Better to add some pullups--it shouldn't take much to clamp
the inputs at a "high" state--100K should be fine. 10K will work fine on
LSTTL.
Cheers,
Chuck
5:57 p.m.
If a tristate buffer is enabled by its control line, but the input to
the buffer is at high-Z is there a typical output?
No, the input will float. _Most_ TTL buffers have inputs that should
float high (so the output will be whatever you should get for a high
input), CMOS ones will pick up random noise. A very few buffers will
float low, I think.
If you require the output to be at a known state under such condtions,
you need to ensure the input is at a known state too, e.g. by adding a
pull-up resistor.
One thing you can be sure of is that the output will not be
high-impedance if the buffer is enabled. The bit of your message that I
deleted seems to suggest you were hoping it would be.
-tony
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