FPGAs and PDP-11's - test-drb@ccmp.vtda.org

27 Aug 1999

On Aug 27, 20:46, Hans Franke wrote:
...
  Subject: Re: FPGAs and PDP-11's
 > Well, the 650x is a VERY thrifty architecture.  It has no memory-to memory
...
  > operations, nor does it have any operations
involving more than one register
...
   at a time.

 TXA ? (Don't kill me :) 
And the indexed instructions such as ADC (nn,X), of course, and TSX, etc.

...
  > much delay per cycle in order to allow the carry
to settle.  Since the ALU
...
  > is used more than once per machine cycle . . .
(see where all this leads?)
...

 More than once ?
 Maybe I'm just blind, but I cant see more than one ALU op per cycle. 
Some of the indexed instructions do.  Once to add the offset, and once for
the operation requested, eg ADC (nn),Y.

-- 

Pete						Peter Turnbull
						Dept. of Computer Science
						University of York