17 Dec
2007
17 Dec
'07
3:58 p.m.
While the subject of delay lines has been hashed out here for a while, most of
the delay lines used in TV sets are probably not too reasonable for data
storage.
In particular those used in NTSC sets are to balance the delays in the chroma
circuits (those that are on the 3.579 sub carrier) with the luma signal (which
isn't processed). Since the chroma goes thru additional circuits, the other
signal needs to be delayed (not very long) to maintain the registration. In
PAL sets, I believe that the same idea is used. The difference is that in PAL
sets a different subcarrier frequency is used, and the demodulation products
are different for every other line (they swap In-phase, and Quadrature). SECAM
is a bit different, as they do NOT use in-phase and quadrature (simultaneous)
demodulation of the color difference signals, but alternate them line by line
(The 'S' in SECAM). This necessitates a one line delay to keep around the
other color difference signal to display on the line. More complexity in the
receiver with all that switching and "storing", and while it has lower color
resolution is more immune to phase differences which plague signal chains in I
& Q (NTSC/PAL) systems. PAL systems on the other hand with the swapping of I &
Q every other line (the 'A' in PAL) usually nulls out the differences.
If you decide to make up a delay line to hold CPU data, try a prototype using
shift registers. They are a bit easier to make up, and often the chips are
available. The problem is that they come in weird (at times) sizes (132, 80,
and the like). I'll leave it to the reader to determine the usability of odd
sizes and their original use.
--
Sorry,
No signature at the moment.
____________________________________________________________________________________
Never miss a thing. Make Yahoo your home page.
http://www.yahoo.com/r/hs
17 Dec
17 Dec
6:06 p.m.
New subject: Shift Registers as Delay Lines (was Delay lines in TV sets)
Tom Watson wrote:
If you decide to make up a delay line to hold CPU
data, try a
prototype using shift registers. They are a bit easier to
make up, and often the chips are available. The problem is
that they come in weird (at times) sizes (132, 80, and the
like). I'll leave it to the reader to determine the
usability of odd sizes and their original use.
A lot of early MOS shift registers were developed specifically for use
in electronic calculators, as solid-state replacements for magnetic core
memory or magnetostrictive delay lines. Since most all electronic
calculators in the mid-'60's through the late 70's operated in BCD or
some alternate four (or sometimes five)-bit representation of decimal
digits, the shift registers were usually made with a number of stages
that was a multiple of four or five, with a few extra bits here and
there for timing and synchronization. That's why many of these devices
as an unusual number of stages. In some calculators from the late
'60's, as IC logic had pretty much replaced discrete transistor designs,
there were different versions of the same machine, earlier machines
which used a magnetostrictive delay line, and "updated" versions which
dispensed with the delay line, and replaced it with a number of MOS IC
shift register devices. Functionally, the machines were identical. As
far as the digital logic section of the machine went, also identical.
The only real changes were the removal of the read amplifier and write
driver for the delay line, and replacement with some simple
level-shifting and power supply circuitry to properly drive the shift
register chain.
Rick Bensene
The Old Calculator Museum
http://oldcalculatormuseum.com
7:08 p.m.
In particular those used in NTSC sets are to balance
the delays in the chroma
circuits (those that are on the 3.579 sub carrier) with the luma signal (which
isn't processed). Since the chroma goes thru additional circuits, the other
signal needs to be delayed (not very long) to maintain the registration. In
PAL sets, I believe that the same idea is used. The difference is that in PAL
It is, but that's not the delay line I'm talking about. Look up the
design of a PAL-D decoder (D = Delay) and see how a
just-less-than-1-line-time delay line is used to store onoe fo the clour
difference signals.
sets a different subcarrier frequency is used, and the
demodulation products
are different for every other line (they swap In-phase, and Quadrature). SECAM
is a bit different, as they do NOT use in-phase and quadrature (simultaneous)
demodulation of the color difference signals, but alternate them line by line
(The 'S' in SECAM). This necessitates a one line delay to keep around the
I thought SECAM was 'Systeme Electronique Couleur Avec Memoire' (?Spel)
The 'M' referes to the delay lien acting as a 1-line time memory to store
one of the colour difference signals I think.
-tony
26 Dec
26 Dec
8:41 p.m.
Tom Watson wrote:
If you decide to make up a delay line to hold CPU
data, try a prototype using
shift registers. They are a bit easier to make up, and often the chips are
available. The problem is that they come in weird (at times) sizes (132, 80,
and the like). I'll leave it to the reader to determine the usability of odd
sizes and their original use.
What about DUAL ported memorys clocked with delay
line speeds?
6054
days inactive
6064
days old
3 comments
4 participants
participants (4)
-
ard＠p850ug1.demon.co.uk -
bfranchuk＠jetnet.ab.ca -
rickb＠bensene.com -
tsw-cc＠johana.com