On 05/13/2011 04:33 PM, Ethan Dicks wrote: Many years back I did a two wire core plane for 16 bytes. I used cores just slightly larger than those in the early PDP8 that some one gave me a load of. To go larger than maybe 64words/bytes it's better to do a three or four wire approach, two half selects and a sense/inhibit line or separate sense and inhibit. I didn't go there as the finest wire I could find was too thick for more than two wires (select and sense). The hardest part was finding the "write current" and Slice or read timing. next step was write and inhibit. One challanege was sensing the valid read after the huge select pulse. it's small compared to the induced pulse What starts to happen as the size of the matrix grows the number of external support parts goes up till you hit some large number like a few K and 4/3 wire geometries. Also you need 1 bit per bit of data (8 for byte 16 for 16bit for example) to hold the captured data during write or read. most system use core as RMW cycle, that is a destructive read, execute, modify if required and then write back. Allison