FPGAs and PDP-11's - test-drb@ccmp.vtda.org

28 Aug 1999

I'm not nearly so concerned about the implementation details. Frankly, the
FPGA vendors are all heading off in the wrong direction for implementation
of those "old" processors and their peripherals.  They give you 10 times
I/O's you need and only half the routing resources.  I'd much rather look at
a plcc44 housing a 2500 CLB FPGA rather than a 500-pin FPGA housing what
they claim is a 400K-gate equivalent.  What's more, I'd rather see a 2
million gate "sea" of gates than a few dozen CLB's or macrocells, providet
there were yards and yards of interconnection resources.  That's not where
they're headed.  They want you to buy 32 ram bits with which to build a
single nand gate.

The PLD vendors aren't any better . . . their devices have always had too
many inputs and not nearly enough buried resources for my taste.  If I have
to "do something" to a couple of inputs based on what a couple more do, then
they work OK, but if I have to do a bunch of well-defined things based on
what one input does, and generate one output based on a complex sequence of
processes, always the same, however, then I have no choice other than the
Scenix SX, which is a microcontroller.  PALs and PLDs have never had the
right input/output pin ratio, nor have they often had sufficient internally
buried registers.  Crying about it won't fix it, though.

Dick
-----Original Message-----
From: Hans B Pufal &lt;hansp(a)digiweb.com&gt;
To: Discussion re-collecting of classic computers
&lt;classiccmp(a)u.washington.edu&gt;
Date: Saturday, August 28, 1999 12:13 PM
Subject: Re: FPGAs and PDP-11's

...
 Richard Erlacher wrote:

> I've taken a good hard look at implementing the 6500 core in XILINX and
find
...
   that
performance, which is VERY much of interest, is impacted most by ALU
 design. 
No-one has mentioned the free IP project at <http://www.free-ip.com/>
which has a VHLD implementation of a 6502 now available. No idea of
performance on this, I have just begun to dabble in this area.

I too bemoan the fact the full configuration specs are not availble for
the FPGA's.
A few years ago I was working for a company that had a Xilinx part
monitoring a processor bus. We wanted to dynamically reconfigure the
FPGA so that we could change the bus pattern it triggered on - no joy
though geting the necessary info.

I see implementing old processors in FPGA's as a way of preserving those
the design of those processors. Yes, we would all prefer to have an
original, but practically speaking that is not possible.

For some uses, a modern re-implementation or an emulator is better than
nothing at all.

Regards

_---_--__-_-_----__-_----_-__-__-_-___--_-__--___-__----__--_--__-___-
Hans B Pufal                          Comprehensive Computer Catalogue
<mailto:hansp@digiweb.com>             <http://digiweb.com/~hansp/ccc> 