19 Jan
2022
19 Jan
'22
8:07 p.m.
So now that my pdp8/L is up and running (it now has a serial port and
runs FOCAL69 quite well) I'm thinking about the next step, which is of
course more memory.
This requires a BA08 or BM8/L or something expansion box but to be
honest I have enough spare flip chips and such from the wrecked 8/I to
build about 3 core memory systems. So given that the schematics for the
BA08 are online, they look pretty darn simple, I have the parts, and I
have the parts does anyone know if it's possible to get a flip chip
backplane to work on and wire up to emulate a BA08?
It looks like they just used the data break interface lines to hook up
to the processor. Everything's there, Memory address bus, memory data
bus, and the various signals for jumps and the like that could allow one
to decode and implement the extra instructions needed.
Hm. Might just be easier to build it with an FPGA or something as it's
mostly linking up simple gates and the whole core memory section could
be removed by a 4k*12 memory array. Anyone ever done this?
C
20 Jan
20 Jan
12:51 a.m.
Not a direct answer Chris, but back in the mid-70's I built a BM8 surrogate the hard
way (we were an impoverished neurophysiology lab so cutting corners wherever reasonable)
using banks of 2102L and S100 RAM PCBs. For density I piggy-backed the 2102's to get
8Kbyte boards, then 3 boards gave 16Kword, so 6 RAM boards were sufficient to fill out the
memory space. The controller was a 1:1 implementation of the DEC schematic, which (if
memory serves) just fit onto a single S100 prototyping board. Cabling from the 8/L was
simple ribbon with alternating grounds. Chassis was ad hoc using a S100 backplane
suitably reinterpreted plus a pair of 8" fans. Added suitable additional DF/IF
switches and lamps to the existing filler-panel and then attached that to the
chassis-front so that it all looked pretty good. It worked for many years without
incident, although AFAIK only core memory was used for execution; the SRAM was used only
for data -- and every added word was taken advantage of :-}.
So there's an existence proof that what you propose isn't unreasonable. I'd
probably have preferred to have a nice backplane and applicable modules to WW, but
point-to-point wiring on the prototyping board worked. Given my skill-set at the time it
was a rather risky venture, but the ROI was excellent. Evidently the DEC design was
forgiving enough that my recreation worked on the first try.
If you decide to pursue the FPGA (or something) approach I'd be interested in doing
the same with my current 8/L. If you go that route, might as well build out all three
bits of DF/IF control even if there may not be any accompanying front-panel.
-----Original Message-----
From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of Chris Zach via cctalk
Sent: Wednesday, January 19, 2022 11:08 PM
To: CCTalk mailing list <cctalk at classiccmp.org>
Subject: Building a BA08 for a pdp8/L
So now that my pdp8/L is up and running (it now has a serial port and runs FOCAL69 quite
well) I'm thinking about the next step, which is of course more memory.
This requires a BA08 or BM8/L or something expansion box but to be honest I have enough
spare flip chips and such from the wrecked 8/I to build about 3 core memory systems. So
given that the schematics for the
BA08 are online, they look pretty darn simple, I have the parts, and I have the parts does
anyone know if it's possible to get a flip chip backplane to work on and wire up to
emulate a BA08?
It looks like they just used the data break interface lines to hook up to the processor.
Everything's there, Memory address bus, memory data bus, and the various signals for
jumps and the like that could allow one to decode and implement the extra instructions
needed.
Hm. Might just be easier to build it with an FPGA or something as it's mostly linking
up simple gates and the whole core memory section could be removed by a 4k*12 memory
array. Anyone ever done this?
C
21 Jan
21 Jan
7:09 p.m.
Hi Paul!
That is really interesting. Did you need to recreate the delay lines or
any of that circuitry, or was it just wire the NAND gates into the chip
address matrix and ignore all the various TP1-TP4 states?
Looking at it I could probably build the basic circuitry on a large
breadboard, I've certainly got the chips from fixing all those M series
boards. That plus a pair of 32k*8 static ram chips from my 386 cache
days and I should be set....
Now where did that big breadboard go?
CZ
On 1/20/2022 3:51 AM, pbirkel at gmail.com wrote:
Not a direct answer Chris, but back in the
mid-70's I built a BM8 surrogate the hard way (we were an impoverished neurophysiology
lab so cutting corners wherever reasonable) using banks of 2102L and S100 RAM PCBs. For
density I piggy-backed the 2102's to get 8Kbyte boards, then 3 boards gave 16Kword, so
6 RAM boards were sufficient to fill out the memory space. The controller was a 1:1
implementation of the DEC schematic, which (if memory serves) just fit onto a single S100
prototyping board. Cabling from the 8/L was simple ribbon with alternating grounds.
Chassis was ad hoc using a S100 backplane suitably reinterpreted plus a pair of 8"
fans. Added suitable additional DF/IF switches and lamps to the existing filler-panel and
then attached that to the chassis-front so that it all looked pretty good. It worked for
many years without incident, although AFAIK only core memory was used for execution; the
SRAM was used only for data -- and every added word was taken advantage of :-}.
So there's an existence proof that what you propose isn't unreasonable. I'd
probably have preferred to have a nice backplane and applicable modules to WW, but
point-to-point wiring on the prototyping board worked. Given my skill-set at the time it
was a rather risky venture, but the ROI was excellent. Evidently the DEC design was
forgiving enough that my recreation worked on the first try.
If you decide to pursue the FPGA (or something) approach I'd be interested in doing
the same with my current 8/L. If you go that route, might as well build out all three
bits of DF/IF control even if there may not be any accompanying front-panel.
-----Original Message-----
From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of Chris Zach via cctalk
Sent: Wednesday, January 19, 2022 11:08 PM
To: CCTalk mailing list <cctalk at classiccmp.org>
Subject: Building a BA08 for a pdp8/L
So now that my pdp8/L is up and running (it now has a serial port and runs FOCAL69 quite
well) I'm thinking about the next step, which is of course more memory.
This requires a BA08 or BM8/L or something expansion box but to be honest I have enough
spare flip chips and such from the wrecked 8/I to build about 3 core memory systems. So
given that the schematics for the
BA08 are online, they look pretty darn simple, I have the parts, and I have the parts
does anyone know if it's possible to get a flip chip backplane to work on and wire up
to emulate a BA08?
It looks like they just used the data break interface lines to hook up to the processor.
Everything's there, Memory address bus, memory data bus, and the various signals for
jumps and the like that could allow one to decode and implement the extra instructions
needed.
Hm. Might just be easier to build it with an FPGA or something as it's mostly linking
up simple gates and the whole core memory section could be removed by a 4k*12 memory
array. Anyone ever done this?
C
22 Jan
22 Jan
8:19 a.m.
I have absolutely no idea! Jameco would have likely been my source for most components
although we did have a Hamilton-Avnet in town and it's possible that ordered some
components from them (I still have a NS databook with their sticker on it). It's
entirely possible that I fiddled with some TTL gate-delays to derive a good-enough
approximation. Where are you getting your circuit schematic from? Maybe if I look at it
a bit something will come back to mind ...
-----Original Message-----
From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of Chris Zach via cctalk
Sent: Friday, January 21, 2022 10:10 PM
To: 'General Discussion: On-Topic and Off-Topic Posts' <cctalk at
classiccmp.org>
Subject: Re: Building a BA08 for a pdp8/L
Hi Paul!
That is really interesting. Did you need to recreate the delay lines or any of that
circuitry, or was it just wire the NAND gates into the chip address matrix and ignore all
the various TP1-TP4 states?
Looking at it I could probably build the basic circuitry on a large breadboard, I've
certainly got the chips from fixing all those M series boards. That plus a pair of 32k*8
static ram chips from my 386 cache days and I should be set....
Now where did that big breadboard go?
CZ
On 1/20/2022 3:51 AM, pbirkel at gmail.com wrote:
Not a direct answer Chris, but back in the
mid-70's I built a BM8 surrogate the hard way (we were an impoverished neurophysiology
lab so cutting corners wherever reasonable) using banks of 2102L and S100 RAM PCBs. For
density I piggy-backed the 2102's to get 8Kbyte boards, then 3 boards gave 16Kword, so
6 RAM boards were sufficient to fill out the memory space. The controller was a 1:1
implementation of the DEC schematic, which (if memory serves) just fit onto a single S100
prototyping board. Cabling from the 8/L was simple ribbon with alternating grounds.
Chassis was ad hoc using a S100 backplane suitably reinterpreted plus a pair of 8"
fans. Added suitable additional DF/IF switches and lamps to the existing filler-panel and
then attached that to the chassis-front so that it all looked pretty good. It worked for
many years without incident, although AFAIK only core memory was used for execution; the
SRAM was used only for data -- and every added word was taken advantage of :-}.
So there's an existence proof that what you propose isn't unreasonable. I'd
probably have preferred to have a nice backplane and applicable modules to WW, but
point-to-point wiring on the prototyping board worked. Given my skill-set at the time it
was a rather risky venture, but the ROI was excellent. Evidently the DEC design was
forgiving enough that my recreation worked on the first try.
If you decide to pursue the FPGA (or something) approach I'd be interested in doing
the same with my current 8/L. If you go that route, might as well build out all three
bits of DF/IF control even if there may not be any accompanying front-panel.
-----Original Message-----
From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of Chris Zach
via cctalk
Sent: Wednesday, January 19, 2022 11:08 PM
To: CCTalk mailing list <cctalk at classiccmp.org>
Subject: Building a BA08 for a pdp8/L
So now that my pdp8/L is up and running (it now has a serial port and runs FOCAL69 quite
well) I'm thinking about the next step, which is of course more memory.
This requires a BA08 or BM8/L or something expansion box but to be
honest I have enough spare flip chips and such from the wrecked 8/I to
build about 3 core memory systems. So given that the schematics for
the
BA08 are online, they look pretty darn simple, I have the parts, and I have the parts
does anyone know if it's possible to get a flip chip backplane to work on and wire up
to emulate a BA08?
It looks like they just used the data break interface lines to hook up to the processor.
Everything's there, Memory address bus, memory data bus, and the various signals for
jumps and the like that could allow one to decode and implement the extra instructions
needed.
Hm. Might just be easier to build it with an FPGA or something as it's mostly linking
up simple gates and the whole core memory section could be removed by a 4k*12 memory
array. Anyone ever done this?
C
4:07 p.m.
There's a couple of MC8/L manuals on bitsavers, this might jog your memory.
http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp8/pdp8l/
Anyway, the timing seems to be for the read core, transfer into MB,
write back into core (because reads are destructive) then send the
completed signal. On MOS memory you probably just need to see the state1
line go high (I have something on the address lines) then just put the
data into the MB and go straight to signal 4 (since you don't need to
rewrite).
On a positive note the 8/L will be able to run as fast as it can as it
doesn't have to wait for the core memory. Hm.
C
On 1/22/2022 11:19 AM, pbirkel at gmail.com wrote:
I have absolutely no idea! Jameco would have likely
been my source for most components although we did have a Hamilton-Avnet in town and
it's possible that ordered some components from them (I still have a NS databook with
their sticker on it). It's entirely possible that I fiddled with some TTL gate-delays
to derive a good-enough approximation. Where are you getting your circuit schematic from?
Maybe if I look at it a bit something will come back to mind ...
23 Jan
23 Jan
1 a.m.
Thank you. I _would have_ probably also looked at the analogous
"MM8I_Schem_Aug69.pdf" print set. But those were antediluvian times; no
Bitsavers and DEC wasn't handing out free print sets. You could purchase them, though
-- I still have KA10 and MA10 documentation that I acquired that way for my own
education/amusement :->.
Fortunately I had access to the full (32Kw MC8-I) controller hard-copy documentation for
the 8/I courtesy of an amazingly built-out system installation in the lab below us (8/I
with a full 32Kw core plus a pair of DF32 plus at least two TU56) who was willing to serve
as my personal lending-library :->. AFAICS that documentation hasn't been captured
in Bitsavers. I have found my 45 y/o 8x11 taped together photocopies if you decide to go
past adding a single additional field. Aside from a few annotations there plus some
sketched connector-signal information I haven't found any as-built documentation --
not even a IC-laydown -- although I see that I used SSM MB6A boards for the SRAM arrays.
Unfortunately no pictures and the system is (very) long gone.
WRT the delay lines, I think that you've nailed it -- my lack of recall is likely
because none of the special timing requirements for the RMW cycle(s) for core applied so I
didn't need to replicate that part of the control; individual R or W cycles based on
the 2102L are necessarily more than fast enough. Unfortunately none of my
implementation-related notes/sketches appear to have survived :-<. And the few that do
are often on the "clean" side of reused paper. Poor church mice ...
I did also find documentation for a MONOSTORE V/PLANAR 1K-word to 8K-word SRAM module
(pub. 1976) for an 8/E that I suspect that I studied carefully to see how OMNIBUS-based
signaling was being handled in an environment where RMW core was also supported. It
claims to have used "AMD DS9408" parts according to the inventory; have never
heard of that one.
In roughly the same time-period I also built-out an AX08 surrogate that went to Appleton,
WI, in support of a newly-minted PhD from our lab. I found some notes relating to the
necessary control components plus the use of "brick" type A/D and D/A devices.
I suspect that the deal was that the new position came with a PO for an 8/I and BA08A
(probably w/o memory), but not an AX08 -- so I was looking for the most cost-effective
means to replicate critical AX08 functionality ... and did so. It's been a long
time.
-----Original Message-----
From: Chris Zach <cz at alembic.crystel.com>
Sent: Saturday, January 22, 2022 7:07 PM
To: pbirkel at gmail.com; 'General Discussion: On-Topic and Off-Topic Posts'
<cctalk at classiccmp.org>
Subject: Re: Building a BA08 for a pdp8/L
There's a couple of MC8/L manuals on bitsavers, this might jog your memory.
http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp8/pdp8l/
Anyway, the timing seems to be for the read core, transfer into MB, write back into core
(because reads are destructive) then send the completed signal. On MOS memory you probably
just need to see the state1 line go high (I have something on the address lines) then just
put the data into the MB and go straight to signal 4 (since you don't need to
rewrite).
On a positive note the 8/L will be able to run as fast as it can as it doesn't have to
wait for the core memory. Hm.
C
On 1/22/2022 11:19 AM, pbirkel at gmail.com wrote:
I have absolutely no idea! Jameco would have likely
been my source for most components although we did have a Hamilton-Avnet in town and
it's possible that ordered some components from them (I still have a NS databook with
their sticker on it). It's entirely possible that I fiddled with some TTL gate-delays
to derive a good-enough approximation. Where are you getting your circuit schematic from?
Maybe if I look at it a bit something will come back to mind ...
831
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days old
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