10 Aug
2009
10 Aug
'09
2:09 p.m.
Roger Ivie <rivie at ridgenet.net> wrote:
I was just remembering the DATI/DATIP/DATO/DATOB transactions, which
can't address the CPU.
I didn't remember that the vector transfer had it's own operation on the
bus.
Nice design really. Yes, once your bus request is granted, you can do
anything on the bus.
Having an adder, or an or with a mask, isn't much different, or
conceptually any more complex in my eye.
But maybe that is just me. :-)
Johnny
--
Johnny Billquist || "I'm on a bus
|| on a psychedelic trip
email: bqt at softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol
On Mon, 10 Aug 2009, Johnny Billquist wrote:
Ah. Yes, I see now (or remember). INTR is a bus transaction, with the
interrupt fielding processor as the implicit slave.
Roger Ivie <rivie at ridgenet.net> wrote:
Second, the vector transfer isn't a normal bus transfer in the sense of the
device addressing the CPU and transferring a word.
Page 2-13 of the UNIBUS spec (1979): "INTR is a bus signal asserted by
an interrupting device *after it becomes bus master* to inform the
interrupt fielding processor that an interrupt is to be performed and
that the interrupt vector is present on the D lines."
Technically, you don't even have an interrupt until the device hands you
the vector. Which it does as a bus master. The CPU cannot
be a slave,
unless my memory fails me.
Page 2-14: "INTR is negated upon receipt of the assertion of SSYN from
the interrupt fielding processor." It's been
way many years since I looked at the unibus map of the VAX UBA, but
I can't for my life imagine that it could be any simpler than the Unibus map
of the PDP-11.
The PDP-11 can map a UNIBUS page to any *word boundary* in the memory
space. That means there are adders in there somewhere. The VAX
scatter/gather map just replaces bits 9 and up with the contents of the
map entry.
5613
days inactive
5613
days old
0 comments
1 participants
participants (1)
-
bqt＠softjar.se