< Well I'm not really a Qbus person. I never got into PDP-11s much and apa < from adding and removing boards from a uVAX-II didn't get to play with Q < much. The sort of thing I'm looking at is a little more sophisticated th < "a bus is something that connects cards together" but a little less bori < than a dry description of arcane features of signal timing and decay < (although I've read plenty of these in my time). let's see if I can do a little on this. Q-bus DECs compaction of Unibus. Qbus is a time multiplexed, asychronous, 16bit data and depending on age of the system 16, 18 or 22 bit address. It has termination and controlled loading to allow operation at high spped using open collector drivers. While a 16 bit bus it also supports various byte transfers. Q-bus is compact and fairly sparce in signals but supports memory, device, interrupt and DMA transfers using the bus data lines and a set of 10 control signals. There are other signals present for processor control such as RUN, PowerOK and Binit are examples. There are more pins than actual signals, some are redundant power for example. There are lines for bus mastering, DMA and interrupt grant/ack are examples. Most devices fall into several loose catagories, IO and memory. The lower 16bits are multiplexed on the bus before every transaction using the same lines data will be transferred on. Cards use BSYNC to capture address and start any bus cycle that pertains to them. Memory is fairly straight forward in that its timed off bsync and will use the other 9 signals to synchronize it's operation. Transactions will be read (word/byte) or write (word/byte). One of the characteristices of PDP-11s is they always read before write (a read modify write cycle is the normal thing). IO devices are identical to memory and by convention and use of BBS7 are located in the top page of the 32KW address space (1 11x xxx xxx xxx xxx). The remaining transacions of not are interrupts and DMA. Interrupts are posted via a request line that can be superceeded by another board physically (buswise) closer to the CPU and will be granted by the CPU to the higest(closest) requestor then and acceeding requesting modules. When an interrupt is granted the board will place a byte(7 bits lowest set to 0) VECTOR on the data bus that the processor will use as a pointer to a table in the first 512byts of ram (interrupts vector table PSW and interrupts service address is located in two words). DMA also has a grant acknowledge and positional priority. Once granted DMA may proceed with byte or word transfers of any length, though generally restricted to short bursts to avoid hogging the bus. The basic signals are: BDAL 0->15-L -L denotes active low signal BSYNC-L BBS7-L Predecoded bank 7 signal (IO bank) BAIKO-L Bus interrupt acknowledge BWTBT-L Bus Write Byte BRPLY-L Bus Cycle reply (must be supplied to continue the cycle or a bus time out error occurs) BDIN-L Bus Data IN toward CPU BDOUT-L Bus Data OUT -> to module Bus cycles have a distinct protocal (sequence) and timings. < Does this narrow it down a little? I'm sort of surprised that there isn' < nice description on the web somewhere.... Me too, though trivial it's not. I tried to avoid a description of each line as that is quite lengthly. Allison