16 Dec
2001
16 Dec
'01
12:56 p.m.
-----Original Message-----
From: Ben Franchuk <bfranchuk(a)jetnet.ab.ca>
After reading the core memory stuff I realized the what I was thinking
about was dynamic memory (16k chips) for a 2 mhz 8080 in byte. The
reason
I got confused was it used the split memory cycle read-write as core
memory.
Core is one of the few destructive readout memories used. So every
read has a following write to restore the data, often between data
read there will be a modify cycle which means new data written back.
Allison
16 Dec
16 Dec
1:20 p.m.
ajp166 wrote:
Core is one of the few destructive readout memories used. So every
read has a following write to restore the data, often between data
read there will be a modify cycle which means new data written back.
I know that. That is why the early memory chips had separate in/out pins
to emulate core memory. Everything nowadays tends to be 8 bits with
tri-state
I/O ( Grumbles here as he has a 12 bit computer and has to waste 4 bits
out of 16 )
BTW - some say the best way to cook a fish is in the dishwasher.
--
Ben Franchuk --- Pre-historic Cpu's --
www.jetnet.ab.ca/users/bfranchuk/index.html
1:51 p.m.
On Sun, 16 Dec 2001, ajp166 wrote:
-----Original Message-----
From: Ben Franchuk <bfranchuk(a)jetnet.ab.ca>
DRAM (well at least 1 T DRAM) is destructive readout also, the
regeneration logic is built into the chip though.
Peter Wallace
After reading the core memory stuff I realized the what I was thinking
about was dynamic memory (16k chips) for a 2 mhz 8080 in byte. The
reason
I got confused was it used the split memory cycle read-write as core
memory.
Core is one of the few destructive readout memories used. So every
read has a following write to restore the data, often between data
read there will be a modify cycle which means new data written back.
Allison
8426
days inactive
8426
days old
2 comments
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participants (3)
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ajp166＠bellatlantic.net -
bfranchuk＠jetnet.ab.ca -
pcw＠mesanet.com