17 Apr
2007
17 Apr
'07
6:28 p.m.
I collected some SCSI specs from the internet before
start the MSCPSCSI
project.
any new news on that?
17 Apr
17 Apr
7:28 p.m.
On 4/17/07, Al Kossow <aek at bitsavers.org> wrote:
Thank you for asking. It worked with NetBSD with no problem. With VMS, It
met a problem that I do not know the cause yet. I compared the messages of
my controller, and the messages of simh (I plugged in some printf()'s in
simh ) when booting VMS CD. It seemed my controller stuck at a place when
VMS installer tried to re-initiate the controller. The SA/SAW communication
did not went through. I post the messages here, to see whether somebody can
give me some suggestions.
In each transaction, bl=scsi CD block number to be read; ba=QBUS memory
address to be written to; bc=number of bytes.
SAR means controller placed a value to SA register for CPU to read; SAW
means CPU wrote SA register. IPW means CPU wrote IP register to reset the
controller.
Messages of my controller:
jumper set to fast DMA; new c94irq installed; EXPECTED_RESET...
drive #0 , 1057758 blocks, 512Bytes/block, SCSI1
drive #1 , 1331808 blocks, 512Bytes/block, SCSI1
drive #2 not detected
drive #3 not detected
rq_scsi[ 0]={rq_ID= 0, scsi_ID= 0, period= 5, offset= 0, blocks=1057758}
rq_scsi[ 1]={rq_ID= 1, scsi_ID= 1, period= 5, offset= 0, blocks=1331808}
SAR=b40
SAR=b40
IPW SAR=b40 SAW=8000 SAR=1080 SAW=1c6 SAR=2000 SAW=0 SAR=4133 SAW=1 SAR=0
bl=1, ba=418, bc=200
...(note: 96 similar lines removed for clarity)
bl=e70a7, ba=4c0, bc=28c0
IPW SAR=b40 SAR=b40
IPW SAR=b40 SAW=8000 SAR=1080 SAW=1e SAR(CONFLICT)=2000 SAW=0 SAR=4133 SAW=1
SAR=0 bl=a2b88, ba=580, bc=200
bl=e74c8, ba=5ac, bc=200
...(note: 166 similar lines removed for clarity)
bl=e6d85, ba=5ac, bc=200
IPW SAR=b40 SAW=a4ff SAR=10a4
IPW SAR=b40 SAW=a4ff SAR=10a4
...(Note: repeat this line for ever. CPU issued IPW to reset the controller;
then controller placed 0xb40 in SA register for CPU to read; CPU wrote to SA
register with 0xa4ff; then controller placed 0x10a4 in SA register for CPU
to read. Then CPU should write SA with another value but it stopped and
reset the controller again and again.)
SIMH messages when booting the VMS CD image:
...(Exactly the same messages as of my controller, until it reached the
point where my controller stuck)
bl=e6d85, ba=5ac, bc=200
IPW SAR=b40 SAW=a4ff SAR=10a4 SAW=c450 SAR=20ff SAW=3 SAR=4133 SAW=403 SAR=0
bl=a2b97, ba=3e194, bc=200
...(it did not stop and reset controller after read 0x10a4, but went on and
wrote SA with 0xc450 instead)
One possibility is that the controller did not place fast enough in SA
register the value CPU was looking for. I need several days to calm down
before I look at this problem again.
vax, 9000
I collected some SCSI specs from the internet
before start the MSCPSCSI
project.
any new news on that?
18 Apr
18 Apr
5:34 a.m.
On 4/17/07, 9000 VAX <vax9000 at gmail.com> wrote:
On 4/17/07, Al Kossow <aek at bitsavers.org> wrote:
Well, my guess is conformed. I observed the QBUS with a logic analyzer and
it seemed the VMS 6.1 installer issued IPW to reset the controller, and
after it read SAR=0x0b40, it wrote SAW=0xa4ff. Then it read SA port at
12.2ms after that, then again at 12.8ms as a second chance, expecting
0x10a4, before it issued IPW again at 12.88ms. My controller had not updated
SAR before the second chance.
The fix seems to be easy. I just need to make sure the controller is able to
update the SAR register quickly. Maybe it is as simple as removing some
printf()'s.
vax, 9000
any new news on that?
One possibility is that the controller did not place fast enough in SA
register the value CPU was looking for. I need several days to calm down
before I look at this problem again. 
20 Apr
20 Apr
4:34 a.m.
New subject: mobygames disbursement
All that and a bag of chips. I have a lot to reply with but it's 10:30
and I'm tired; I'll give you a call tomorrow or Saturday.
Brian Hirt wrote:
On 4/17/07, 9000 VAX <vax9000 at gmail.com>
wrote:
--
Jim Leonard (trixter at oldskool.org) http://www.oldskool.org/
Help our electronic games project: http://www.mobygames.com/
Or check out some trippy MindCandy at http://www.mindcandydvd.com/
A child borne of the home computer wars: http://trixter.wordpress.com/
On 4/17/07, Al Kossow <aek at bitsavers.org> wrote:
Well, my guess is conformed. I observed the QBUS with a logic analyzer and
it seemed the VMS 6.1 installer issued IPW to reset the controller, and
after it read SAR=0x0b40, it wrote SAW=0xa4ff. Then it read SA port at
12.2ms after that, then again at 12.8ms as a second chance, expecting
0x10a4, before it issued IPW again at 12.88ms. My controller had not
updated
SAR before the second chance.
The fix seems to be easy. I just need to make sure the controller is
able to
update the SAR register quickly. Maybe it is as simple as removing some
printf()'s.
vax, 9000
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any new news on that?
One possibility is that the controller did not place fast enough in SA
register the value CPU was looking for. I need several days to calm down
before I look at this problem again.
4:42 a.m.
New subject: mobygames disbursement
My apologies; this was the result of Thunderbird seriously freaking out.
Sorry for the confusion!
Jim Leonard wrote:
All that and a bag of chips. I have a lot to reply
with but it's 10:30
and I'm tired; I'll give you a call tomorrow or Saturday.
Brian Hirt wrote:
--
Jim Leonard (trixter at oldskool.org) http://www.oldskool.org/
Help our electronic games project: http://www.mobygames.com/
Or check out some trippy MindCandy at http://www.mindcandydvd.com/
A child borne of the home computer wars: http://trixter.wordpress.com/
On 4/17/07, 9000 VAX <vax9000 at gmail.com>
wrote:
On 4/17/07, Al Kossow <aek at bitsavers.org> wrote:
Well, my guess is conformed. I observed the QBUS with a logic analyzer
and
it seemed the VMS 6.1 installer issued IPW to reset the controller, and
after it read SAR=0x0b40, it wrote SAW=0xa4ff. Then it read SA port at
12.2ms after that, then again at 12.8ms as a second chance, expecting
0x10a4, before it issued IPW again at 12.88ms. My controller had not
updated
SAR before the second chance.
The fix seems to be easy. I just need to make sure the controller is
able to
update the SAR register quickly. Maybe it is as simple as removing some
printf()'s.
vax, 9000
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any new news on that?
One possibility is that the controller did not place fast enough in SA
register the value CPU was looking for. I need several days to calm down
before I look at this problem again.
6487
days inactive
6490
days old
4 comments
3 participants
participants (3)
-
aek＠bitsavers.org -
trixter＠oldskool.org -
vax9000＠gmail.com