see below, plz Dick ----- Original Message ----- From: "Allison" <ajp166(a)bellatlantic.netTo: <classiccmp(a)classiccmp.orgSent: Tuesday, December 18, 2001 10:49 AM Subject: Re: MITS 2SIO serial chip? post feature, There Yes, that's true, though the "deleted data address mark" was an IBM standard feature. Western apparently though it might be useful to write unique address marks. Why? I don't know. Western did the stepper timing, but I still can't understand why they didn't build in the head-load timer. There was talk about stuff like that, but all the WD chips did was (1) return the result of and ID read, or (2) set a flag to ensure the track in the ID field was consistent with the track register content. Timing is everything, isn't it? I think what happened was that someone gave me one of the early 1793's and I was off and running, since I already had used the 1771 and had code that would work with it. NEC had a couple of earlier controllers, numbered something like 371 and 372, didn't they? > >vs packet programming though. Perhaps you could cite an example? The > Western > >part is certainly register based. Isn't the NEC part also just a register > set? > Internally the 765 has "registers". However, you feed it via one port > addres with a > command packet and after the data IO is done you read a status packet of 1-9 > bytes > based on the command issued. It's obvious when you look at the part, the > 765 > has A0 for the port addressing (status and command/data) where A0 only has > meaning{it's only active during /CS not /DACK) during non-dma ops. > >That was an advantage for those who were invested in a software base, but > nobody > >knew that back in '78-79. What's the 36C766? Google comes up empty. I've > seen > >some 37C665/666 types, but 36Cnnn? Who made them? > Several vendors including SMC and UMC. They were variations of the 765 with > rate generators and interface to disk plus IOports (parallel, serial and > even IDE). > Aimed at PCs they replaced the two serial ports, IDE, FDC and parallel > boards. > >What's interesting, BTW, is that even Western, with its institutional > prejudice > >toward analog PLL's went with the 765 core once it went to the fully > integrated > >all-digital FDC, having dealt with the lower data rates in the 1770/72/73 > chips, > >which were not shown to be capable of 500 Kbps for some reason. Perhaps > there > >was some advantage in the 765 core that made it more amenable to > integration > >with a digital clock extraction circuit at the higher data rate. I doubt > that > >Intel would have gone for the 765 type if there weren't some manufacturing > >advantage inherent in the silicon. That may be what's made the difference. > >Intel certainly would have chosen the chip that was more economically > >manufacturable, though maybe their primary economy came from the > >already-established relationship (which they'd sabotage later) with NEC. > The 765 core did the step rate and many of the external things that the 1793 > needed external hardware for. The preference for digital data seperation > was > pushed by NEC as it could be done with a small 32x4 prom and a latch with > good reliability compared to the often difficult analog designs. Also > digital > fits on silicon of the time better. I have a design and samples we did in > late > '81 to put the floppy side "glue" on one 2500 gate array that allowed for > data > sep, write pre comp, drive and motor selects and all the other things that > would end up on the super chips. The end result was a complete FDC two > chip combo that was half the price of discrete 765 or WD 1793 designs with > no performance compromizes. It was never marketed for obtuse reasons > and less than three years later several vendors were putting 765+glue on > one chip. > And the d7265 was the ISO 3.5" tuned version that had a shorter VCO sync > time{post index gap time} and a shortend index gap. I believe most of the > 765 cores are of the 7265 flavor. > The aside to that is that the SMC 9229 was a digital data sep/clock/precomp > that worked with both the 765 and 1793 with equal perfomance for all rates. > SMC also had a 765 core with analog PLL (9265 or 66) for those that prefered > analog. The 1770/2/3 problem was not data seperator in itself but process > speed > of the die, they{WD} flat out could not do the required 16mhz stuff then for > the > data sep and the other rate generators. The 1793 with external 9229 works > great at 500khz but, the 1793 only has to see something like 2 or 4mhz max > and therein lies the difference. That was 2 MHz. So it was the process, eh? I was curious how this played in the outside world. Western was happy enough to take my all-digital circuitry that worked just fine from an 8 MHz clock, BTW, but they didn't use it, and I always figured that was because they'd entered into a second-source arrangement with SMC, which came up with the 9216 and 9229. The 9229, btw, cost quite a bit more than the simple logic I used for the clock selection, data/clock separation, and write precomp, not to mention head load timeout. The space reduction did make it appealing, though. My own stuff was well firmed up by then , however, and I didn't ever use the 9229 until much later, when I was using up sample stock on onesies.