I want to play with a russian K1801BM2 CPU (K1801VM2). My russian from the school is very very rusty and so I have problems to understand what's going on with this CPU while startup. There is some "besadresnoe tschtanie", a read from the bus w/o sending out an address before w/o active SYNC. It is right, that this read is building the upper 8 bits from the start address in the rom area with Systemu Mode (Halt Mode) = 1? Can anyone please confirm this? BTW: how is this external register to be done in HW? Does anyone know if there are schematics of SBCs existing w/o special support ICs like The K1801VP1-55 or so? Kind Regards and thanks in advance, Holm -- Technik Service u. Handel Tiffe, www.tsht.de, Holm Tiffe, Freiberger Stra?e 42, 09600 Obersch?na, USt-Id: DE253710583 www.tsht.de, info at tsht.de, Fax +49 3731 74200, Mobil: 0172 8790 741