On 5/11/05, Holger Veit <holger.veit at ais.fraunhofer.de> wrote: I have a quantity of INS8073 docs, including a National App Note that describes a reference system with a couple of 2114 SRAMs, an op amp as a level shifter (can use MAX232, or 1488/1489 if you have +/-12V handy). It uses three? resistors to implement the INS8073 baud rate jumpers (110, 1200, 4800) - they pull certain data lines one way or the other when reading a non-existent memory address around $FC00 or so. The internal ROM code interprets the byte read to select a baud rate. It's a trivial chip to make a minimal system from - RAM, TTL-to-EIA conversion, and baud-rate resistors. An expanded system isn't much harder; I have an MC-1N board that I reverse engineered before tracking down the maker (who is still around in the embedded market). His design uses a 32x8 PROM as an address selector. It specifically selects no devices at that magic $FC00 (I think) block so that the resistors can be properly sensed (i.e., no valid device is also trying to drive the bus). The MC-1N has a 24-pin RAM socket (6116, nominally), a 24-pin ROM socket (2732 EPROM), some National clock/calendar chip, and an 8255 PPI chip for I/O. The MC-1N manual described how to set/read the clock and how to fiddle the 8255 lines. I'm part of the way through a hand-wired knock-off of the MC-1N, but I haven't had the time to finish. I'm thinking I'm going to want to whip up a 16V8 GAL to replace the PROM since I have wads of GALs and no tiny PROMs. To more specifically answer your console I/O question, there are, ISTR, three input flag lines and two output flag lines. One each of them is taken over by the code in the internal ROM and used for communicating with the BASIC interpreter. I _think_ one of the manuals mentions that as long as you never PRINT or INPUT, you can steal those lines back for user-defined I/O, but it is not recommended. Write me off-line and let me know how I can throw several hundred Kbytes at you. -ethan