23 Aug
2005
23 Aug
'05
3:26 p.m.
Subject: Re: Floppy controller questions
From: Philip Pemberton <philpem at dsl.pipex.com>
Date: Tue, 23 Aug 2005 22:47:06 +0100
To: cctalk at classiccmp.org
In message <0ILO00FI3MXS1LM0 at vms048.mailsrvcs.net>
Allison <ajp166 at bellatlantic.net> wrote:
They are right. MFM requres twice the clock of FM as it's twice the speed.
Obvious to me. However the statement is valid as the APPLIED clock is 2X
the DATA rate for any mode.
One of the confusing issues the fact that when going to MFM (AKA Double Density)
you will always run the clock twice that of FM but the ratios of Wclock to data
rate is always 2. The MFM pin can be used to select Wclock or Wclock/2 for
MFM/FM operation on write and for read it can select clock or other timing
dependent control for the read_data and read_data_window recovery.
Oh and BTW: those specified data rates would be for 8" drives. For 5.25
they are half that.
Write clock sets the write data rate and should
corrospond to the
rate needed for media. Writeclock is 2x data rate.
Does this apply to both FM and MFM? The datasheet suggests a 500kHz WrClk for
FM and 1MHz for MFM mode, which would give a 250kHz FM data rate and a 500kHz
MFM data rate. Is that right? And RdWindow from the datasep should cover the read
frequency variations,
assuming the datasep can handle the variation in mode and frequency.
Assuming you condition the data seperator for the correct mode with
MFM output from the FDC.
the logic does
things like Data Clock recovery, Write precompensation timing
I've heard the term "write precompensation" thrown about a bit - what's
the
purpose of it? Using a 765
for _all_ data rates and both 3.5"/5.25"/8" floppy interfaces
implemented with LSttl fills a S100 board completly.
That's why SPLDs (GALs) and CPLDs were invented I guess. Squish the address
decoder, interface logic, and the data separator into a few LSTTLs and GALs,
or just throw everything into a single CPLD :) Most designs
implemented a subset for 8" or 5.25"/3.5" only
(jumper selected) with much lower parts cost.
That's what I wanted. I don't have any 8" drives, so adding support for them
is pointless. Ideally, I want a board that has a 6502-type interface on one
side and a 34-pin IDC connector on the other, with support for most common FM
and MFM 3.5" and 5.25" formats. Yes, it was
done on the 1.2MB AT-class machines. Reminder: every PC with
rare exceptions used a 765 or a derivitive based on the 765 core.
So I've noticed. I managed to get DMA-mode transfers working, but never
managed to get polled-mode or interrupt-mode transfers working. Guess I'll
have to learn fast when I start writing code to drive the FDC... For MFM is
when the transiston occurs rather than how many. Generally the
Floppy generates what is by standard expected and the FDC external logic
will regenerate data pulses and data window (data window is a read clock).
Right. So with FM the datasep syncs to the high-frequency signal in Gap1,
then every time there's a 0 you'll pick up a 0/1/0/1 sequence for each read
window, and when there's a 1 you'll pick up a 1/1/1/1 sequence?
And with MFM, a 0 after a 0 would be 1/0, a 0 after a 1 would be 0/0 and a 1
would be 0/1?
0/1 taken to mean "first data window was empty, second had a pulse in it".
More like a 0 was a longer window than a one. where the FM the window
always has one transistion and if it's a one then there will be a
transistion near the middle of the window.
The trick with floppies is the drive has a narrow bandwidth and the typical
data rate must be in the range of F and 2F where F is some number of flux
transistion per unit time (and also realated to per inch at rotation speed).
MFM does some long string things to get the number of transistions to stay
within F and 2F bit does not have the clear 1:1 symbol corolation of FM.
Of course in real life not much of this is needed to assemble a working
FDC/Floppy interface.
Allison
23 Aug
23 Aug
3:22 p.m.
Write clock sets the write data rate and should
corrospond to the
rate needed for media. Writeclock is 2x data rate.
Does this apply to both FM and MFM? The datasheet suggests a 500kHz WrClk for
FM and 1MHz for MFM mode, which would give a 250kHz FM data rate and a 500kHz
MFM data rate. Is that right? >> Using a 765 for _all_ data rates and both
3.5"/5.25"/8" floppy interfaces
>> implemented with LSttl fills a S100 board completly.
>
>That's why SPLDs (GALs) and CPLDs were invented I guess. Squish the address
I always thought they were invented to make my job more painful than it
should be ;-)
decoder,
interface logic, and the data separator into a few LSTTLs and GALs,
or just throw everything into a single CPLD :)
Yep, helped design and test a mask programmed gate array that reduced the
minimal base PC from about 15 chips to less than 7 while keeping a good
data sep and write precomp logic. Most
designs implemented a subset for 8" or 5.25"/3.5" only
(jumper selected) with much lower parts cost.
That's what I wanted. I don't have any 8" drives, so adding support for them
is pointless. Ideally, I want a board that has a 6502-type interface on one
side and a 34-pin IDC connector on the other, with support for most common FM
and MFM 3.5" and 5.25" formats. 
4:46 p.m.
In message <m1E7h9n-000IyXC at p850ug1>
ard at p850ug1.demon.co.uk (Tony Duell) wrote:
Also be aware that many HD-capcable 5.25" drives
turn at 360 rpm all the
time. Which means the data rate if you put a DD (or for that matter an
SD) disk in them is 6/5 times what you'd get with that disk in a DD drive
(which turns at 300 rpm). You may well need to provide a suitable clock
for 300 kbps, for example.
Ick. Time to find a 24MHz crystal oscillator :-/
Divide by 3 gives 8MHz, div24 for 1MHz, div48 for 500kHz, div96 for 250kHz.
And none of those are powers of two. Yay. I think I'll just stick to 8MHz and
1M/500k write clocks.
I always thought they were invented to make my job
more painful than it
should be ;-)
Only if you're trying to reverse engineer something :)
I hate ASICs too, unless they're fully documented down to gate level in some
way. The CBM 1541 is a great example... Version 1 was all TTL, v2 had an ASIC
to do the GCR coding, v3 had an ASIC that did the GCR *and* analogue
interfacing IIRC. Ick.
I still need to deal with the "only 16uS to grab a byte of data" issue.
That's going to be a major pain when the CPU is running at 2MHz... Thankfully
IDE/ATA is fairly speed independent.
I suppose I could use interrupt mode, and hijack the INT (or maybe the NMI)
vector whenever the FDD is being accessed.
Isn't learning fun?
data separators. And I've seen a board of logic
(the original IBM
controller, for example). But I've never seen a real 765 linked to an
I really should try and get a copy of the IBM PC Technical Reference manuals
at some point.
Unless you are using the original Sony 3.5"
drives, which turn at 600
rpm, and thus use twice the data rate you might expect, 5.25" drives and
3.5? drives use the same data rates for the same modes.
All new-ish PC-type floppy drives here. I don't think I've got any of the
original Sony drives - most of mine are MFD920s, with one or two MFD520s (I
prefer the 520s - they're jumperable for DS0 and ideal for RiscPCs). Some of
the Citizen drives that Acorn used are pretty well made, too - I've never
seen one that didn't work properly. Well, except for the one that some oik
(not me) shoved a mini-CD into.
HD disks (1.2Mbyte, 1.44Mbyte respectively) in their
approriate drives
use the same data rates as 8". SD and DD disks are half of those rates
_apart from the 360rpm issue I mentioned above).
Easy way to solve the 360rpm issue: Find the SPEED_SEL pin on the motor
controller, lift the pin then wire it to the edge connector.
I
FWIW, 3" are the same as those too (there never
was a HD 3" disk AFAIK).
Heh. Amstrad 3" "indestructable" floppies. Those bring back some
memories...
Mostly dealing with disintegrating drive belts.
--
Phil. | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem at philpem.me.uk | Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/ | Panasonic CF-25 Mk.2 Toughbook
... I'm spending a year dead for Tax Purposes
4:39 p.m.
In message <m1E7h9n-000IyXC at p850ug1>
ard at p850ug1.demon.co.uk (Tony Duell) wrote:
Indeed. As you've probably spotted by now, some of the all-in-one-chip PC
disk controllers need a 24MHz clock for just that reason.
Also be aware that many HD-capcable 5.25"
drives turn at 360 rpm all th=
e=20
time. Which means the data rate if you put a DD
(or for that matter an=20
SD) disk in them is 6/5 times what you'd get with that disk in a DD dri=
ve=20
(which turns at 300 rpm). You may well need to
provide a suitable clock=
=20
for 300 kbps, for example.
Ick. Time to find a 24MHz crystal oscillator :-/ Divide by 3 gives 8MHz, div24 for 1MHz, div48 for
500kHz, div96 for 250kH=
z.
There's a well-known divide-by-3 circuit using a couple of JKs...
And none of those are powers of two. Yay. I think
I'll just stick to 8MHz=
and
1M/500k write clocks.
Or repair it. I have a lot more luck finding an obscure TTL part than
finding an ASIC, or the right CPLD + the data to program into it +
somebody who can actually program the thing
I always thought they were invented to make my
job more painful than it=
=20
should be ;-)
Only if you're trying to reverse engineer something :) I hate ASICs too, unless they're fully documented
down to gate level in s=
ome
way. The CBM 1541 is a great example... Version 1 was all TTL, v2 had an =
ASIC
to do the GCR coding, v3 had an ASIC that did the GCR *and* analogue
interfacing IIRC. Ick.
I found the Sams repair manual for the 1541 many years ago in a
second-hand bookshop in Bristol. Of course I bought it. It covers 3
versions of the drive (which they call the 1540, 1541, 1542, although
AFAIK those names are not all official). There's some data on the ASIC
(which replaces a load of TTL + a ROM in the original version. I don't
recall there being any analagoue ASIC stuff in those drives, but IIRC the
1570 and 1571 do have a hybrid circuit that's part of the analogue side,
and is custom/unrepairable.
data
separators. And I've seen a board of logic (the original IBM=20
controller, for example). But I've never seen a real 765 linked to an=20
I really should try and get a copy of the IBM PC Technical Reference manu=
als
at some point. Unless you are using the original Sony 3.5"
drives, which turn at 600=20
rpm, and thus use twice the data rate you might expect, 5.25" drives an=
d=20
3.5=A3 drives use the same data rates for the
same modes.
All new-ish PC-type floppy drives here. I don't think I've got any of the
original Sony drives - most of mine are MFD920s, with one or two MFD520s =
(I HD disks
(1.2Mbyte, 1.44Mbyte respectively) in their approriate drives=20
use the same data rates as 8". SD and DD disks are half of those rates=20
_apart from the 360rpm issue I mentioned above).
Easy way to solve the 360rpm issue: Find the SPEED_SEL pin on the motor
controller, lift the pin then wire it to the edge connector.
I
Actually, I think the 3" disk is mechancially better than the 3.5" one.
I've never had an Amstrad drive, I used the Hitachi ones (I even have the
offiical service manual for the double-head version), which had a
direct-drive spindle motor.
-tony
FWIW, 3" are the same as those too (there
never was a HD 3" disk AFAIK).
Heh. Amstrad 3" "indestructable" floppies. Those bring back some
memories=
...
Mostly dealing with disintegrating drive belts.
7063
days inactive
7063
days old
3 comments
3 participants
participants (3)
-
ajp166＠bellatlantic.net -
ard＠p850ug1.demon.co.uk -
philpem＠dsl.pipex.com