MITS 2SIO serial chip? - test-drb@ccmp.vtda.org

18 Dec 2001

From: Ben Franchuk &lt;bfranchuk(a)jetnet.ab.ca&gt;
...

Having looked at a few other Floppy disk datasheets for the pc, I would
suspect
it needs a 24 Mhz clock. I can divide this by 2 to give me 12 Mhz clock
for the 

Either some product of 9.6mhz (for the oddball 1.2mb 5.25 floppies) or some
product of 16mhz for the 500khz 1.44mb floppy.  That is of course for the
floppy side interface only.  The CPU side is driven by Tacc for the FDC IO
ports (4 or 8mhz depending on part and age) and the data rate for read
or write since there is no silo on the parts I know of.  This will be true
for all
765 based FDCs (most of the PC controllers are 765 or 765 core logic).

Data rates for 1.44mb floppy are the worst at 13uS first byte and 16uS
for the remaining.

If DMA is possible do it.  If not can the cpu execute a wait state during
IO{wait
on data ready with the read or write pending}?  If neither of those then you
have
to loop and test status or worse usually, use interrupts.

It's possible to find WD FDC drivers around but they will be very machine
specific more often than not.

Allison