Possibly it's a variation of the Lancaster TVT (Cheap Video) design? What is it?

And it's waht I suspect too... Indeed. That was a very common trick to have 2 650x CPUs in parallel. It's how the CBM IEEE-488 disk drives were designed, for example. You need a mux on the address lines (because the CPU does not tri-state those between memory accesses), but you can tie the data lines together. Think of the 6507 as (very) programmable counter chain (in the simplest case just have it executing NOPs and JMPs). That's the video address logic. And you could probably get it to pulse the high-order address lines (by jumping up there and back again) to generate sync signals. I once had this idea (which I've never followed up) to use a common, fast, 8 bit processor with no instruction pipelining (so you know what the buses are doing and when) as a microcode sequencer. Just give it 8+n bit wide memory, with the 8 bits consisting of NOPs and (conditional) jumps. the n bits are the control lines to whatever you're microcoding. -tony