21 Mar
2018
21 Mar
'18
7:19 p.m.
There are enough pdp8 fpga that they have started to calll themselves
YAPDP8FPGA.
So what are the really good FPGA DEC processors?
-chuck
21 Mar
21 Mar
9:47 p.m.
I?ve been working on updating my DEC emulation site, that includes the FPGA section. That
might help you find some, I?m sure that I have plenty of gaps.
http://www.avanthar.com/healyzh/decemulation/pdp_fpga.html
Zane
Sent from my iPod
On Mar 21, 2018, at 7:19 PM, Charles Dickman via
cctalk <cctalk at classiccmp.org> wrote:
There are enough pdp8 fpga that they have started to calll themselves
YAPDP8FPGA.
So what are the really good FPGA DEC processors?
-chuck
22 Mar
22 Mar
2:35 a.m.
On 21/03/18, Zane Healy via cctalk wrote:
I?ve been working on updating my DEC emulation site,
that includes the FPGA section. That might help you find some, I?m sure that I have
plenty of gaps.
http://www.avanthar.com/healyzh/decemulation/pdp_fpga.html
I'd like to add mine to the list:
I've done a PDP-6 (not tested very much, but that should change soon):
https://github.com/aap/pdp6/tree/master/verilog
...and am currently working on a KA10:
https://github.com/aap/pdp10
My goal is to stay as close to the original schematics as possible.
That means I'm simulating delay elements with counters and stuff like
that. Also note that these two projects are the only experience with
HDLs that I have. Don't expect them to be very professional.
aap
5:36 a.m.
Sent from my iPod
On Mar 22, 2018, at 2:35 AM, Angelo Papenhoff via
cctalk <cctalk at classiccmp.org> wrote:
Thanks! I?m traveling for work this week so it will take a while to update.
Zane
On 21/03/18, Zane Healy via cctalk wrote:
I?ve been working on updating my DEC emulation site, that includes the FPGA section.
That might help you find some, I?m sure that I have plenty of gaps.
http://www.avanthar.com/healyzh/decemulation/pdp_fpga.html
I'd like to add mine to the list:
I've done a PDP-6 (not tested very much, but that should change soon):
https://github.com/aap/pdp6/tree/master/verilog
...and am currently working on a KA10:
https://github.com/aap/pdp10
My goal is to stay as close to the original schematics as possible.
That means I'm simulating delay elements with counters and stuff like
that. Also note that these two projects are the only experience with
HDLs that I have. Don't expect them to be very professional.
aap 
9:40 a.m.
On 03/22/2018 05:47 AM, Zane Healy via cctalk wrote:
I?ve been working on updating my DEC emulation site,
that includes the FPGA section. That might help you find some, I?m sure that I have
plenty of gaps.
http://www.avanthar.com/healyzh/decemulation/pdp_fpga.html
Zane
Here is mine for the list, a PDP-1 (and some optional PDP-1D features)
in Verilog:
https://github.com/Jside/pdp1
It is a behavioral implementation rather than a gate-by-gate one.
So it is easy to read and debug but not accurate in the instruction
"pipeline" or timings.
- Jan
12:03 a.m.
2249
days inactive
2249
days old
6 comments
6 participants
participants (6)
-
aap＠papnet.eu -
aek＠bitsavers.org -
chd＠chdickman.com -
healyzh＠avanthar.com -
jan＠janadelsbach.com -
lars＠nocrew.org