Captain Napalm <spc(a)armigeron.com> wrote: Slow architecture results in commercial failure. But it was incredibly neat. It could best be characterized as a VCISC; it had a *much* more complex architecture than a VAX. Part of the reason it was slow was that they were pushing the limits of 1980 technology to fabricate it, so they couldn't actually fit the main processor (GDP, for General Data Processor) onto a single chip. They had to split it into two chips, of which the 43201 was the instruction decoder and microsequencer, and the 43202 was the execution unit. Unfortunately due to packaging limitations the microinstruction bus between the two chips was not wide enough to support single-cycle microinstruction execution. The 432 was a capability-based architecture. Objects were divided into two portions, an access part and a data part. The access part could only store access descriptors (pointers to other objects), while the data part could store anything but access descriptors. This allowed efficient implementation of Dijkstra's parallel garbage collection. Unfortunately each part of the object is limited to 64 kilobytes. Intel claimed that the 432 was designed for Ada. Actually, it was designed before Ada, and it merely happened that Ada proved to be a particularly suitable language for it. However, the first HLL for the 432 that Intel provided to customers was a variant of Rosetta Smalltalk called OPL: http://www.rosetta.com/TechHistory.html#opl-432 432 GDP instructions were of variable size, from 6 to 344 bits, depending on the number of operands (0-3) and the addressing modes. Intel had an assembler for the DECsystem-10, but never shipped it to customers. The cross-development environment for Ada ran on the VAX. The 432 GDP did not do an I/O operations. There was a 43203 IP (Interface Processor), which was used in conjunction with an AP (Attached Processor), typically an 8086. The IP wasn't really a processor in the conventional sense of the word, in that it didn't execute stored programs. It executed commands provided by the AP in order to control five memory windows that allowed the AP to access objects in the 432 memory space. The 432 supported 16 megabytes of physical memory, and an extremely large virtual space. Intel designed a persistent object store as part of the iMAX-432 operating system, however the persistent object store implementation was never shipped to customers. Other chips in the 432 set included the 43204 BIU (Bus Interface Unit) and 43205 MCU (Memory Control Unit). Using the complete chipset, it was easy to design systems with full fault-tolerance. All of the chips were designed to be usable in pairs to support FRC (functional redundancy checking), in which one component was the master and one was the checker. The checker performed exactly the same computations as the master, but instead of driving bus signals, it compared its own results with those of the master, and signalled an error if there was a mismatch. The master and checker roles were exchanged on alternate bus cycles in order to insure that there were no latent faults in the checker. FRC alone isn't enough to build a fault-tolerant system, because if a failure is detected, it is not known which of the two components failed. So pairs of FRC modules could be operated in lock step for QMR (Quad Modular Redundancy). When an FRC pair fails, the board is disabled and the other board is known to have valid state. Under the direction of software, several recovery methods were possible. The remaining module could continue operating without a backup, in which case the system is no longer fault-tolerant. The module could be shut down, in which case the system is still fault-tolerant but has lower performance. Or the module could be paired with a spare module reserved for that purpose. The hardware provided mechanism, but the software determined the policy. Although it is out of print, the most easily found reference on the 432 is _A_Programmer's_View_of_the_Intel_432_System_ by Elliot Organick. Anyone still have any 432 docs, hardware, or software? Cheers, Eric