22 Dec
2010
22 Dec
'10
1:15 p.m.
Chuck writes:
I pointed it out because (a) the Intel i860 was yet
another stumble
by Intel to get away from the 8008 architecture (the 432 being only a
slightly earlier one--and one in a diametrically opposite direction)
and the application (cluster) was novel.
Personally I always thought the i860 was far from a stumble, because in
fact it was the highest MFlops/dollar and MFlops/watt for a considerable
length of time and used in a number of high-horsepower applications
in the real world.
Farms/clusters weren't awful novel, scientists had been assembling their
own for a decade before. Intel seeing that it could commercialize a massively
parallel computer, yes in some people's eyes that would make it legit
(when somehow it wasn't legit whenever anyone did it in the decades before...?)
Maybe by some measures i860 was a stumble because it didn't replace
x86 but by those measures, everything is a failure. Hardly seems like
a good definition of success. Aka "Where Are We Going? Planet Ten!
When Are we Going? Real Soon!"
Tim.
22 Dec
22 Dec
2:01 p.m.
Personally I always thought the i860 was far from a
stumble, because in
fact it was the highest MFlops/dollar and MFlops/watt for a considerable
length of time and used in a number of high-horsepower applications
in the real world.
And Intel sure sold quite a few i860s. I would bet that most i860s
ended up as coprocessor cards in PeeCees, where they did one task and
did not run into the dreaded pipeline flush context switch problem.
--
Will
5:26 p.m.
Personally I
always thought the i860 was far from a stumble, because in
fact it was the highest MFlops/dollar and MFlops/watt for a considerable
length of time and used in a number of high-horsepower applications
in the real world.
And Intel sure sold quite a few i860s. I would bet that most i860s
ended up as coprocessor cards in PeeCees, where they did one task and
did not run into the dreaded pipeline flush context switch problem. 
6:11 p.m.
The i860 was in:
Stardent Vistra
AT&T 3d PC accelerator card for TOPAS
both failed in the marketplace, this was the year of the 25MHz Compaq that was almost as
fast, at least running TOPAS. I think the Vistra held on for a bit with Weitek vector
processor supporting it. Stardent (Kubota Computer Graphics) was the largest computer
failure and bankruptcy at the time, late 80s.
From: spectre at floodgap.com
Subject: Re: Uncommon: Intel Paragon on iOffer
To: cctalk at classiccmp.org
Date: Wed, 22 Dec 2010 14:26:52 -0800
I know I've seen i860s in graphics boards. I think one of the NeXTs used
them as well.
--
------------------------------------ personal: http://www.cameronkaiser.com/ --
Cameron Kaiser * Floodgap Systems * www.floodgap.com * ckaiser at floodgap.com
-- Out of my mind (back in an hour). ------------------------------------------
Personally I always thought the i860 was far from a stumble, because in
fact it was the highest MFlops/dollar and MFlops/watt for a considerable
length of time and used in a number of high-horsepower applications
in the real world.
And Intel sure sold quite a few i860s. I would bet that most i860s
ended up as coprocessor cards in PeeCees, where they did one task and
did not run into the dreaded pipeline flush context switch problem. 
9:36 p.m.
On Dec 22, 2010, at 5:26 PM, Cameron Kaiser <spectre at floodgap.com> wrote:
I know I've seen i860s in graphics boards. I think one of the NeXTs used
them as well.
I don't recall seeing any i860s in NeXT hardware. What was on the NeXTDimension
board? It has been too long since I've seen one.
Some high-end SGI graphics subsystems for their Ebus machines use big arrays of i860s.
-Dave
--
Dave McGuire
Port Charlotte, FL
Personally I always thought the i860 was far from a
stumble, because in
fact it was the highest MFlops/dollar and MFlops/watt for a considerable
length of time and used in a number of high-horsepower applications
in the real world.
And Intel sure sold quite a few i860s. I would bet that most i860s
ended up as coprocessor cards in PeeCees, where they did one task and
did not run into the dreaded pipeline flush context switch problem. 
23 Dec
23 Dec
4:34 p.m.
On Wed, 22 Dec 2010 21:36:00 -0500
Dave McGuire <mcguire at neurotica.com> wrote:
I don't recall seeing any i860s in NeXT hardware.
What was on the NeXTDimension board?
Yes, NeXTdimension. See:
http://www.levenez.com/NeXTSTEP/NeXTdimension.pdf
http://en.wikipedia.org/wiki/NeXTdimension
--
\end{Jochen}
\ref{http://www.unixag-kl.fh-kl.de/~jkunz/}
4:46 p.m.
On Wed, 22 Dec 2010 21:36:00 -0500
Dave McGuire <mcguire at neurotica.com> wrote:
Some high-end SGI graphics subsystems for their Ebus
machines use
big arrays of i860s.
Well. The Extreme GFX for the 1st generation (teal R4k based)
Indigo2
puts 8 i860 geometry engines in a desktop machine...
--
\end{Jochen}
\ref{http://www.unixag-kl.fh-kl.de/~jkunz/}
5:02 p.m.
On 12/23/10 4:46 PM, Jochen Kunz wrote:
Those aren't i860s, they're custom chips. Big ones.
Did they implement the i860 architecture?
The Extreme video subsystem is really nice.
-Dave
--
Dave McGuire
Port Charlotte, FL
Some high-end
SGI graphics subsystems for their Ebus machines use
big arrays of i860s.
Well. The Extreme GFX for the 1st generation (teal R4k based)
Indigo2
puts 8 i860 geometry engines in a desktop machine...
28 Dec
28 Dec
11:59 a.m.
On Thu, 23 Dec 2010 17:02:06 -0500
Dave McGuire <mcguire at neurotica.com> wrote:
As far as I have googled they are just
i860 dice, four in a big
multichip package. AFAIK the Extreme GFX is just the same as the Elan
GFX of the Indigo, but with more geometry engines.
Well. The
Extreme GFX for the 1st generation (teal R4k based) Indigo2
puts 8 i860 geometry engines in a desktop machine...
Those aren't i860s, they're custom chips. Big ones.
Did they implement the i860 architecture? The Extreme video subsystem is really nice.
Well. Impact is nicer and VPro even nicer...
(I shoud get a Fuel some day...)
--
\end{Jochen}
\ref{http://www.unixag-kl.fh-kl.de/~jkunz/}
23 Dec
23 Dec
3:01 p.m.
And Intel sure
sold quite a few i860s. I would bet that most i860s
ended up as coprocessor cards in PeeCees, where they did one task and
did not run into the dreaded pipeline flush context switch problem.
I know I've seen i860s in graphics boards. I think one of the NeXTs used
them as well. 
22 Dec
22 Dec
2:12 p.m.
On 22 Dec 2010 at 13:15, Shoppa, Tim wrote:
Personally I always thought the i860 was far from a
stumble, because
in fact it was the highest MFlops/dollar and MFlops/watt for a
considerable length of time and used in a number of high-horsepower
applications in the real world.
Don't get me wrong--I thought the i860 was remarkable from an
architectural standpoint and familiar stomping ground for an old
supercomputer guy. But Intel just had no idea of how to market it.
Himself BillG even gave it some happy words (but then, what products
of Intel didn't he give happy words to?).
Farms/clusters weren't awful novel, scientists had
been assembling
their own for a decade before. Intel seeing that it could
commercialize a massively parallel computer, yes in some people's eyes
that would make it legit (when somehow it wasn't legit whenever anyone
did it in the decades before...?)
I can't remember who I first heard it from (Neil Lincoln or Nix
Frazier, perhaps) to the effect that massively parallel computing was
like trying to take nine women and get a baby in one month.
I view the Paragon as being in the same category as the Sequent boxes
of about the same timeframe. Nice for a collector to own, and not
requiring its own HVAC or chilled-water supply and still within the
range of residential electrical service capabilities.
--Chuck
7:25 p.m.
On Wed, 22 Dec 2010, Chuck Guzis wrote:
Himself BillG even gave it some happy words (but then,
what products
of Intel didn't he give happy words to?).
He called the 80286 "brain dead"!
I remember Gordon Letwin (Microsoft OS/2) describing switching back and
forth between real and protected mode as being "like having to turn off
your engine to switch gears on the freeway".
--
Grumpy Ol' Fred cisin at xenosoft.com
7:33 p.m.
He called the 80286 "brain dead"!
Was anything alive on that? ;oD
I remember Gordon Letwin (Microsoft OS/2) describing
switching back and
forth between real and protected mode as being "like having to turn off
your engine to switch gears on the freeway".
Well, that is the way it actually happens...but instead of turning off,
you just disconnect it :)
So, the autohydraulic transmission is the pentium of the cogboxes? :oD
8:29 p.m.
On 22 Dec 2010 at 16:25, Fred Cisin wrote:
On Wed, 22 Dec 2010, Chuck Guzis wrote:
I assume this was before the LOADALL instruction was discovered. I
wonder if Letwin's statement was designed to confuse the competition,
since you"d think that Microsoft would be on the Intel developer
distribution list...
--Chuck
Himself BillG even gave it some happy words (but
then, what products
of Intel didn't he give happy words to?).
He called the 80286 "brain dead"!
I remember Gordon Letwin (Microsoft OS/2) describing switching back
and forth between real and protected mode as being "like having to
turn off your engine to switch gears on the freeway". 
9:09 p.m.
On 12/22/2010 5:29 PM, Chuck Guzis wrote:
On 22 Dec 2010 at 16:25, Fred Cisin wrote:
Developers didn't know about it. A friend of mine found and documented
it. It was not even in the Red covers for the processor.
Some other friends at Micro 5, who were writing a clone of the 286 bios
for their clone and the emm driver found that microsoft knew about it by
discovering it in their code, which could do protected mode entry /
exits and data transfers as a result "too fast" They disassembled and
reverse engineered the method and included it in their driver, which
when discovered caused a big fuss because intel thought they had
violated IP, (they were not nondisclosed).
And it was brain dead to do that. By the way, the loadall was in there
at all to support the bondout package version used in ICE. Up to that
time, INtel never had done a bondout chip special for any of their ice
products, but used the same die with more signals for that purpose.
Other vendors of ICE had to do elaborate things to support the ICE
function if it was doable at all.
Jim
On Wed, 22 Dec 2010, Chuck Guzis wrote:
I assume this was
before the LOADALL instruction was discovered. I
wonder if Letwin's statement was designed to confuse the competition,
since you"d think that Microsoft would be on the Intel developer
distribution list...
--Chuck
Himself BillG even gave it some happy words (but
then, what products
of Intel didn't he give happy words to?).
He called the 80286 "brain
dead"!
I remember Gordon Letwin (Microsoft OS/2) describing switching back
and forth between real and protected mode as being "like having to
turn off your engine to switch gears on the freeway". 
23 Dec
23 Dec
4:23 a.m.
jim s wrote:
Up to that time, INtel never had done a bondout chip
special for any
of their ice products, but used the same die with more signals for that
purpose.
I think you may be mistaken about that. Some of Intel's ICE products
for their single-chip micros used special bondout chips that brought out
signals not bonded out on the normal parts. These were for the 8048 and
8051 series parts. The early versions of the ICE for the 8048 did use
standard parts, and that caused problems where the ICE didn't behave
exactly the same as the masked-ROM part.
If I recall correctly, the special 8051 bond-out chip actually taped out
before the normal masked ROM and the EPROM version.
I suspect that there were special bondout chips for other related parts,
such as the 8021, 8041, etc., but I didn't use the corresponding ICE
products so I don't have any firsthand knowledge about those.
Eric
12:07 p.m.
On Dec 22, 2010, at 6:09 PM, jim s wrote:
On 12/22/2010 5:29 PM, Chuck Guzis wrote:
There was a separate document that described it.
On 22 Dec 2010 at 16:25, Fred Cisin wrote:
Developers didn't know about it. A friend of mine found and documented it.
It was not even in the Red covers for the processor. On Wed, 22 Dec 2010, Chuck Guzis wrote:
I assume this was
before the LOADALL instruction was discovered. I
wonder if Letwin's statement was designed to confuse the competition,
since you"d think that Microsoft would be on the Intel developer
distribution list...
--Chuck
Himself BillG even gave it some happy words (but
then, what products
of Intel didn't he give happy words to?).
He called the 80286 "brain
dead"!
I remember Gordon Letwin (Microsoft OS/2) describing switching back
and forth between real and protected mode as being "like having to
turn off your engine to switch gears on the freeway".
Some other friends at Micro 5, who were writing a clone of the 286 bios for their clone
and the emm driver found that microsoft knew about it by discovering it in their code,
which could do protected mode entry / exits and data transfers as a result "too
fast" They disassembled and reverse engineered the method and included it in their
driver, which when discovered caused a big fuss because intel thought they had violated
IP, (they were not nondisclosed).
Several of us at IBM were doing "interesting" things with the loadall
instruction on the 286. The 386 also had a variation of the loadall instruction but with
the introduction of the vm86 mode, the major need to use (outside of Intel) the loadall
instruction was obviated.
And it was brain dead to do that. By the way, the loadall was in there at all to support
the bondout package version used in ICE. Up to that time, INtel never had done a bondout
chip special for any of their ice products, but used the same die with more signals for
that purpose. Other vendors of ICE had to do elaborate things to support the ICE function
if it was doable at all.
The loadall instruction was a "test" instruction (Intel does similar things on
most of their parts). It allowed them to load all of the state of the processor at once.
It simplified their testing of the part.
The ICE parts were special bondouts/fuse versions of the part (Intel still does that
today...but for different SKUs...no more ICE). When you start getting into high frequency
buses it's just not feasible. Looking at the FSB analyzers for Core & Core 2
parts it was amazing that they worked at all (the analyzers). How to you probe every
signal on a high pin count 1GHz+ bus? It's not easy and the equipment is $$$$$$$.
The ICE functionality has been replaced with a JTAG like interface/protocol.
TTFN - Guy
1:53 p.m.
On 22 Dec 2010 at 18:09, jim s wrote:
Developers didn't know about it. A friend of mine
found and
documented it. It was not even in the Red covers for the processor.
Actually, I find that entirely believable. We were working with the
early steppings of the 186. We also had early steppings of the 286
in-house but hadn't done much other than test real-mode operation;
Intel was working on the kernel for Xenix; In retrospect, I wonder if
the Intel Xenix team even knew about the LOADALL instruction.
Anyway, back to the 186.
I recall took us about 2 weeks to track down one such nasty bug, all
while our Intel apps contact sort of stood by with his hands in his
pockets. When we informed him of the bug, the response from the chip
development group was "oh yeah, we knew about that a couple of weeks
ago".
Communication within Intel was terrible by the time it got to the
customer. And Bill Davidow was on our board of directors, so it
wasn't as if we didn't have any influence.
--Chuck
4960
days inactive
4966
days old
17 comments
13 participants
participants (13)
-
ard＠p850ug1.demon.co.uk -
cclist＠sydex.com -
cisin＠xenosoft.com -
eric＠brouhaha.com -
ggs＠shiresoft.com -
jkunz＠unixag-kl.fh-kl.de -
jws＠jwsss.com -
mcguire＠neurotica.com -
pu1bzz.listas＠gmail.com -
rdawson16＠hotmail.com -
spectre＠floodgap.com -
tshoppa＠wmata.com -
wdonzelli＠gmail.com