3 Apr
2002
3 Apr
'02
6:41 a.m.
Right off, let me say that I know next to nothing about the realities of
using core memory. I only know that it looks like pretty cool stuff to
play with. Would I be completely off my tree to try to build a core
memory interface from scratch, assuming I had a pre-strung core frame with
all the cores and wires intact? When I say "interface", I mean basically
something that will let me talk to the core from a PC or from my
recently-completed Mark-8 using TTL or CMOS levels. If I have a 64x64
frame, would I just need something on the order of 256 driver transistors
(one to drive each of the X and Y wires in either direction) plus some
kind of op-amp or comparator circuit to monitor the sense wire (is there
just one of these per frame?) and determine whether or not a bit has
flipped during a read pulse? Or are there all sorts of ghosts and goblins
lurking in core memory that I don't want to confront?
3 Apr
3 Apr
8:02 a.m.
Bill Richman wrote:
Right off, let me say that I know next to nothing about the realities of
using core memory. I only know that it looks like pretty cool stuff to
play with. Would I be completely off my tree to try to build a core
memory interface from scratch, assuming I had a pre-strung core frame with
all the cores and wires intact? When I say "interface", I mean basically
something that will let me talk to the core from a PC or from my
recently-completed Mark-8 using TTL or CMOS levels. If I have a 64x64
frame, would I just need something on the order of 256 driver transistors
(one to drive each of the X and Y wires in either direction) plus some
kind of op-amp or comparator circuit to monitor the sense wire (is there
just one of these per frame?) and determine whether or not a bit has
flipped during a read pulse? Or are there all sorts of ghosts and goblins
lurking in core memory that I don't want to confront?
At one time they made CORE memory driver IC's for driving the lines.
If you can find any of the old guys they would be handy.
--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html
9:08 a.m.
Bill,
You're a man after my own heart! I've been thinking about this for some time. I
once had some NICE small core planes (16k I think) out of a HP communications analyzer and
I think they would have been just about perfect for this. I had too many other projects at
the time so I sold them but I know where there are some more analyzers so I may grab them
and swipe the core from them. I found the service manual for the analyzer so I had the
pin out for the entire machine including the core. (I still have it). IIRC the core module
was about 5 inches square and had all the drivers and sense amps on it so that might make
things easier. However there are some things that you have to do with core and I don't
know if they handled in hardware or if the OS had to take care of it. For example, reading
core is destructive, that is it erases the contents so you have to store the contents back
into it before you do anything else (unless you don't care if it's lost). That
seems like it would be easy enough to do in HW but I don't know if that's what
they did.
Joe
At 11:41 AM 4/3/02 -0600, you wrote:
Right off, let me say that I know next to nothing about
the realities of
using core memory. I only know that it looks like pretty cool stuff to
play with. Would I be completely off my tree to try to build a core
memory interface from scratch, assuming I had a pre-strung core frame with
all the cores and wires intact? When I say "interface", I mean basically
something that will let me talk to the core from a PC or from my
recently-completed Mark-8 using TTL or CMOS levels. If I have a 64x64
frame, would I just need something on the order of 256 driver transistors
(one to drive each of the X and Y wires in either direction) plus some
kind of op-amp or comparator circuit to monitor the sense wire (is there
just one of these per frame?) and determine whether or not a bit has
flipped during a read pulse? Or are there all sorts of ghosts and goblins
lurking in core memory that I don't want to confront?
9:27 a.m.
Having the drivers is important. I've looked in vain
for the 75xxx series chips described in the famous
1976-ish Byte Magazine article on core memory that has
been mentioned before. Without those, its a heck of a
lot of discretes, and there's no way around it. Too
bad, because I have some really nice core memory with
the diodes only that deserves to do more than hang on
a wall. I also suspect that because of all of the
unknowns involved regarding the magnetic properties of
the core that you use, the way to go about it is to
put a lot of pots on a single driver/receiver setup,
tweek em to the middle, and repeat. My understanding
of core is that there are thermistors involved also,
and that core had a very narrow range of temperature
operation. There were even programs designed
specifically to cause "hot spots" in the core in order
to test it (you'd have to know the physical layout of
the core to pull this trick off).
--- Joe <rigdonj(a)cfl.rr.com> wrote:
Bill,
You're a man after my own heart! I've been
thinking about this for some time. I once had some
NICE small core planes (16k I think) out of a HP
communications analyzer and I think they would have
been just about perfect for this. I had too many
other projects at the time so I sold them but I know
where there are some more analyzers so I may grab
them and swipe the core from them. I found the
service manual for the analyzer so I had the pin out
for the entire machine including the core. (I still
have it). IIRC the core module was about 5 inches
square and had all the drivers and sense amps on it
so that might make things easier. However there are
some things that you have to do with core and I
don't know if they handled in hardware or if the OS
had to take care of it. For example, reading core is
destructive, that is it erases the contents so you
have to store the contents back into it before you
do anything else (unless you don't care if it's
lost). That seems like it wou!
ld be easy enough to do in HW but I don't know if
that's what they did.
Joe
At 11:41 AM 4/3/02 -0600, you wrote:
__________________________________________________
Do You Yahoo!?
Yahoo! Tax Center - online filing with TurboTax
http://taxes.yahoo.com/
Right off, let me say that I know next to nothing
about the realities of
using core memory. I only know that it looks like
pretty cool stuff to
play with. Would I be completely off my tree to
try to build a core
memory interface from scratch, assuming I had a
pre-strung core frame with
all the cores and wires intact? When I say
"interface", I mean basically
something that will let me talk to the core from a
PC or from my
recently-completed Mark-8 using TTL or CMOS
levels.
If I have a 64x64
frame, would I just need something on the order of
256 driver transistors
(one to drive each of the X and Y wires in either
direction) plus some
kind of op-amp or comparator circuit to monitor
the
sense wire (is there
just one of these per frame?) and determine
whether
or not a bit has
flipped during a read pulse? Or are there all
sorts of ghosts and goblins
lurking in core memory that I don't want to
confront?
9:47 a.m.
Response from a seller I asked about the core planes he's selling (and I'm
bidding on) on eBay. Can I beat him like a baby seal? Please...? Just
for a little while...? "I disposed of the driver boards," indeed. I'd be
"afraid" too. <sigh> The driver boards probably weren't
"pretty" enough
to fetch a good price from the "collectors" on eBay. If you're gonna
salvage _some_ of it, get the _whole_thing_! "I'm sorry, Mr. Smith - I'm
afraid I 'disposed of' the bank routing number on the check I sent you for
the core planes." (Don't get me wrong here - I'm not saying he's the
least bit dishonest, but I hate it when someone is cavalier about having
gotten rid of something I wanted!) <*cry>
They are perfect. No damaged cores or wires. I'm
afraid I disposed of
the driver boards.
4:57 a.m.
On Wed, 3 Apr 2002, Bill Richman wrote:
> They are perfect. No damaged cores or wires.
I'm afraid I disposed of
> the driver boards.
This is the same kind of guy who would capture and kill a rhinocerous just
so he could saw off it's dick and grind it up to make a tea.
Sellam Ismail Vintage Computer Festival
------------------------------------------------------------------------------
International Man of Intrigue and Danger http://www.vintage.org
* Old computing resources for business and academia at www.VintageTech.com *
11:43 a.m.
Joe wrote:
Bill,
You're a man after my own heart! I've been thinking about this for some time. I
once had some NICE small core planes (16k I think) out of a HP communications analyzer and
I think they would have been just about perfect for this. I had too many other projects at
the time so I sold them but I know where there are some more analyzers so I may grab them
and swipe the core from them. I found the service manual for the analyzer so I had the
pin out for the entire machine including the core. (I still have it). IIRC the core module
was about 5 inches square and had all the drivers and sense amps on it so that might make
things easier. However there are some things that you have to do with core and I don't
know if they handled in hardware or if the OS had to take care of it. For example, reading
core is destructive, that is it erases the contents so you have to store the contents back
into it before you do anything else (unless you don't care if it's lost). That
seems like it wou!
!
ld be easy enough to do in HW but I don't know if
that's what they did.
Writing back to memory was a hardware function. Clear memory and
Incriment/Decriment memory were often implimented as memory write back
features.
--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html
4 Apr
4 Apr
8:53 a.m.
Core memory has another complication ........
Reading a core memoryline from the matrix means you also
have to write the line back because reading from core memory
is a data destructive operation. This means that any read cycle
is in fact a read+write memory cycle. This has also concequences
for the total speed of subsequent read operations (like a program
running from core). The read access may be reasonably fast but
the next read cycle can only start after the internal write-cycle
has completed................
A kind of page interleave may solve this problem but:
Obviously you'll have to cook up all the extra logic to execute
all this in hardware ..............
Regards,
Sipke de Wal
---------------------------------------------------------
http://xgistor.ath.cx
---------------------------------------------------------
----- Original Message -----
From: Bill Richman <bill(a)timeguy.com>
To: <classiccmp(a)classiccmp.org>
Sent: Wednesday, April 03, 2002 7:41 PM
Subject: Core Memory Interfacing?
Right off, let me say that I know next to nothing
about the realities of
using core memory. I only know that it looks like pretty cool stuff to
play with. Would I be completely off my tree to try to build a core
memory interface from scratch, assuming I had a pre-strung core frame with
all the cores and wires intact? When I say "interface", I mean basically
something that will let me talk to the core from a PC or from my
recently-completed Mark-8 using TTL or CMOS levels. If I have a 64x64
frame, would I just need something on the order of 256 driver transistors
(one to drive each of the X and Y wires in either direction) plus some
kind of op-amp or comparator circuit to monitor the sense wire (is there
just one of these per frame?) and determine whether or not a bit has
flipped during a read pulse? Or are there all sorts of ghosts and goblins
lurking in core memory that I don't want to confront?
8141
days inactive
8142
days old
7 comments
6 participants
participants (6)
-
bfranchuk＠jetnet.ab.ca -
bill＠timeguy.com -
foo＠siconic.com -
rigdonj＠cfl.rr.com -
sipke＠wxs.nl -
sloboyko＠yahoo.com