On Tue, 26 Aug 1997, Kevin McQuiggin wrote: OK... The convention is very logical when you get used to it. In general, a pin number consists of 4 parts, normally a number, a letter in the range A-F, a letter in the range A-U, and a number in the range 1-2. Sometimes the first 2 parts are swapped round, giving the letter first. OK. The first number tells you which card on the backplane to look at. If you are looking at the board side of the backplane with the component side of the cards on the right (the normal way up), then slot 1 is on the right. For example, on a PDP11/44, slot 1 contains the M7090 card (and sometimes the M7091). On an 11/45, slot 1 contains the M930 terminator, the KW11-L line time clock (I forget the M-number), and the KM11 test connectors. The first letter tells you which connector in the slot to look at. A is the top/rearmost slot, F is the bottom/front one. Taking the 2 examples above, the M7090 or M930 cards go in connectors A and B. Note that a quad card (like many SPC cards) fits into connectors C-F. DEC were _not_ consistent here - some printsets for such cards call the connectors on the board C-F, others call them A-D. It's normally indicated on the overlay diagram in the printset, though. The second letter tells you which of the 18 pins on one side of the connector to look at. This uses the 'DEC Alphabet' where some characters were left out to avoid confusion with badly printed manuals, etc. The sequence is A B C D E F H J K L M N P R S T U V . A is the top/rearmost pin (closest to slot A). The last digit gives the side of the board. 1 is the component side, 2 is the solder side. Note that most of the signals are _active low_. I think grants are just about the only exception to this. OK, from memory, the main ones are : A0-A17 - Unibus Address lines D0-D15 - Unibus Data lines PA,PB - Parity control lines (memory parity, per byte?) C0,C1 - Control lines. Indicate one of 4 bus cycles - Word Write, Byte Write, (Word) Read, Word Read, but don't restore memory contents MSyn - Master Sync. A signal from the bus master, telling the slave to look at the address/data/control lines. Think of it as being like a 68000 DS* SSyn - Slave Sync. A signal from the slave to the master indicating that it recognises the address. Like DTACK on a 68000 BRn - Bus Request - signal from peripheral to indicate it wants to cause a interrupt BGn - Bus Grant - signal to the peripheral indicating that it can output a interrupt vector. Note that each slot has BG in and BG out lines. The interrupting peripheral does _not_ pass on the grant, all others do. So the peripheral nearest to the CPU has the highest priority. Intr - Interrupt. Signal output by the peripheral along with an interrupt vector, indicating that it is a vector on the bus NPR - Non-Processor Request. A DMA request line NPG - Non-Processor Grant. DMA Grant line, used like BGn above. SACK - Select acknowledge. Used to indicate that the peripheral has received the grant and is taking the bus Gnd - Ground, 0V, etc +5V, +15V, -15V - Obvious! ACLO, DCLO - power fail signals from the PSU to the system LTC - Pulse that occurs every mains cycle, used by the real time clock. -tony

Hi Tony: My new MJ3000 arrived today, I'll install it and let you know whether my +15 returns. Thanks for your assistance, Kevin -- Kevin McQuiggin VE7ZD mcquiggi(a)sfu.ca