22 Mar
2012
22 Mar
'12
1:17 a.m.
Pertec is a pretty simple interface with handshake lines. I would
imagine you shouldn't have much trouble. An FPGA may be overkill
(certainly harder to work with 5v); you may find it even easier to
just use a microcontroller. My Cipher F880 runs on just a Z80
internally, nothing fancier than that.
My understanding of the protocol is the drive sets the speed it spits
out bytes,
and that it can be up to 1 Mbyte/sec. There is no handshaking, the read
data
is just clocked out as the feels like. I don't see how a Z80 can keep up
with that unless your formatter runs a lot slower. In theory, GCR data
coming off the drive at 75 IPS can flow in bursts up to 480,000 byte/sec.
(GCR actually records 6400 9-bit characters/inch, the 6250 refers to
the equivalent data byte density after the ECC redundancy data is removed.)
Your F880 is of course a slower drive and maybe 800/1600 only, so the
data rate can be much lower.
I have a product that uses a Xilinx FPGA connected through
the PC parallel port in EPP mode, and have used it as a development
board for several oddball projects, and so a good deal of code reuse
makes this an easier path for me. The only extra job is I have to add
a buffer SRAM to my board as the on-FPGA memory is not enough
to hold the largest tape block permitted.
Jon
22 Mar
22 Mar
6:21 p.m.
On 21 Mar 2012 at 20:17, Jon Elson wrote:
I have a product that uses a Xilinx FPGA connected
through
the PC parallel port in EPP mode, and have used it as a development
board for several oddball projects, and so a good deal of code reuse
makes this an easier path for me. The only extra job is I have to add
a buffer SRAM to my board as the on-FPGA memory is not enough to hold
the largest tape block permitted.
My Chi/Computer Logics ISA controller has 256K of memory organized as
a ring buffer with 16-bit DMA handling the transfer to CPU-local
memory. It's pretty successful in keeping up with medium-fast (75
ips) streamers, but I suspect that it would fall down on 150 ips
drives.
My first attempt at a DIY Pertec used a PCI data aquisition card with
three 8255s on it. Only moderately successful using a Fuji X2444--a
controller-local buffer is very desirable. If you happen to have a
well-stocked junkbox with some FIFOs in it, that would certainly
help.
Long block tapes have been an anathema for a long time. A block can
theoretically be as long as an entire reel of tape, which means that
if there is lost data during transfer (either because of the CPU to
controller link or the inability of the CPU program to accept data
fast enough), you have to backspace to the IRG and start again. I
spent a lot of frustrating time working with CDCs 1LT driver on half-
reel long blocks.
Short blocks, on the other hand, were fun--you could make music with
the drive, the pitch depending on the block size.
--Chuck
7:05 p.m.
On Thu, 22 Mar 2012, Chuck Guzis wrote:
On 21 Mar 2012 at 20:17, Jon Elson wrote:
I think that's the same unit I have, along with a Qualstar 1052
transport.
It came with Qualstar software, but no particular technical information on
the interface card as I recall.
--
I have a product that uses a Xilinx FPGA
connected through
the PC parallel port in EPP mode, and have used it as a development
board for several oddball projects, and so a good deal of code reuse
makes this an easier path for me. The only extra job is I have to add
a buffer SRAM to my board as the on-FPGA memory is not enough to hold
the largest tape block permitted.
My Chi/Computer Logics ISA controller has 256K of memory organized as
a ring buffer with 16-bit DMA handling the transfer to CPU-local
memory. It's pretty successful in keeping up with medium-fast (75
ips) streamers, but I suspect that it would fall down on 150 ips
drives.
4735
days inactive
4735
days old
2 comments
3 participants
participants (3)
-
cclist＠sydex.com -
elson＠pico-systems.com -
snhirsch＠gmail.com