Hi.
Josh Dersch <derschjo at mail.msu.edu> wrote:
I'm still trying to figure out what's gone
wrong with the unibus on my
11/40. To recap -- the machine is responsive if I run it without a
terminator at the end of the bus; with a terminator installed the front
panel is unresponsive. I've checked the following:
- The NPG grants are continuous from the front to the back.
- There are grant continuity cards in each empty slot.
- I am running with a minimal configuration (only CPU and 64K MOS memory)
I made one final discovery about two months ago -- the SPC slot in slot
9 of the main CPU backplane (which I am 100% sure is an SPC slot and not
some special-purpose slot) does not work properly. I cannot get the
Console SLU/LTC board to function when installed in slot 9 (which is
where it's typically installed, or so I hear). It works fine in other
unibus slots.
That is not a good sign.
I have three questions, any help on these would be,
well... helpful.
I'm hoping to have some time to play around with it in the coming months.
1) Is the NPG grant on the SPC slot on the processor backplane (slot 9)
supposed to be connected to the NPG grants on the Unibus expansion?
That is -- right now if I set my DMM to continuity mode and put one
probe on CA1 on the first slot of the unibus expansion, and the other on
CB1 on the last slot of the unibus expansion, since all NPG grant
jumpers are in place, the DMM shows the circuit as closed. This is as
I'd expect. However, if I move the probe from CA1 on the first slot of
the expansion to CA1 on slot 9 of the processor backplane, the circuit
is then open. I'm guessing this is not correct. (There is currently an
NPG jumper installed on slot 9.) All other grant lines seem to be
continuous.
That sounds really bad. NPG should originate from the CPU (unless my
memory fails me), and pass through each SPC slot. If it don't even make
it to the first slot (slot 09 of the CPU box) then you'll never get a
working system.
But how can you have a connection from CB1 out from the CPU slot 9, but
not a connection from CA1 out, when you do have a jumper between CA1 and
CB1 (of slot 9)? That sounds like a broken jumper to me.
2) Where is the +15V to the processor backplane
supposed to be
connected? (I suspect this may be the reason the SLU won't function in
slot 9...). Right now it's plugged into pin CV1 on slot 9 (if I'm
reading the Unibus pin chart right :)) but the docs I have found say
this should be ACLO_L...
Have you measured? Is it +15V, or +5V? ACLO_L is active low, and if you
have a good AC in, then I would expect that pin to be +5V in that case.
Afraid I can't help more right now. Any description of an SPC slot
should tell you, but I'm not sitting next to any manuals right now.
3) Does anyone have a wirelist for the 11/40 CPU
backplane (or is this
in any of the service/reference manuals)? Worst case, I can probe out
the wiring and figure out what's missing/incorrect on slot 9.
Sorry that I can't help more on this one. Didn't see any on bitsavers.
Maybe someone else have them?
Johnny
--
Johnny Billquist || "I'm on a bus
|| on a psychedelic trip
email: bqt at softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol