11 Dec
2008
11 Dec
'08
11:40 p.m.
Subject: Re: Bootstrappable language
From: "bfranchuk at jetnet.ab.ca" <bfranchuk at jetnet.ab.ca>
Date: Thu, 11 Dec 2008 12:27:12 -0700
To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>
Dave Dunfield wrote:
Have you lookd at DG Nova? Sounds like your traversing that same path.
You don't need register to register
operations to support a C compiler.
Can you provide any details of your architecture and instruction set?
It might be feasable to make a port of my Micro-C toolset to it... If
not, it might be feasable to make a port of "C-flea" a virtual machine
I designed specifically to support Micro-C (I've supported some pretty
weird architectures by employing C-flea).
The architecture is like I said before a stretched PDP-8, with a
512 byte direct addressing range and more compleate set of alu operations.
I am exploring the idea that 18 bits is still the best size word size
for a small computer or digital controller. The extra opcode bit
is used to
support word &
byte sized operands, compared to the that of a 8 bit micro. The two more
address
bits negate the loss of byte addressing and give a bit more room for a
resident
OS rather than swapping core in and out.
Using CPLD's also gives me the feel that a 18 bit simple cpu like my design
could have been developed as microchip computer similar to 6800 or 6502
chip set around the time the Z80 was developed. Using 48 rather 40 pins
as packaging a 18 bit cpu with front panel support could have been
developed.
A) Cpu chip. B) Swr/data/address bus display support chips . C)
data/byte swap buffer.
A table driven assembler can produce anything.
Also a stack based language or even C can have the anythig stack related as
multiple instructions only code efficientcy suffers and code size.
An alternate way to go is a small emulation engine written in assebler to emulate
a easier to compiler for virtual machine (P-code).
The IDE can be 9 bits as the upper 8 (or less) bits are only used for data and a
non required ops. I've done that for 8bits to simplify the interface and the
only cost is 50% of the data space was not used, a minor nit as I had 500%
more than needed.
Allison
Micro-C is a very small, but reasonably powerful
dialect of C - For an
example, refer to the ImageDisk sources on my site ... ImageDisk and all
of it's utilities are compiled with the PC version of Micro-C (as are my
simulators, transfer tools and pretty much all of the other DOS based
tools I've posted).
Dave
Btw: If you haven't written an assembler yet, let me know - I've got a
universal table driven assembler generator which I developed to rapidly
produce assemblers for many of the later architectures I supported.
Unlikely it will work , I have 9 bit bytes.
I have hacked, Jones's PDP 8 assembler to cross assemble for me.
Once I get the the single PCB board built later next year, then I
will consider porting Micro-C. I plan to only have about 64Kb +
bootstrap EEPROM, IDE interface and a two 6850 uarts
along with a front panel. I am not sure yet if the IDE interface will be
16 or 9 bits wide yet.
14 Dec
14 Dec
5:33 p.m.
Allison wrote:
Have you lookd at DG Nova? Sounds like your
traversing that same path.
Yes and NO!
A table driven assembler can produce anything.
99% of the code I have seen assumes 8 bit bytes.
I have decided to a 20 bit cpu ... 10 bit bytes. So far every thing
seems to fit in the CPLD's I can get, but it is not done until
I get all the bugs checking done, as right now it is more hacking
as I go with the logic.
Try Idea, it fits , fix new bug, it don't fit, start over again.
The IDE can be 9 bits as the upper 8 (or less) bits
are only used for data and a
non required ops. I've done that for 8bits to simplify the interface and the
only cost is 50% of the data space was not used, a minor nit as I had 500%
more than needed.
I plan to do it that way ... Just I/O lines on the CPLD's are very limited.
Allison
7:41 p.m.
On 14 Dec 2008 at 10:33, bfranchuk at jetnet.ab.ca wrote:
99% of the code I have seen assumes 8 bit bytes.
I have decided to a 20 bit cpu ... 10 bit bytes. So far every thing
seems to fit in the CPLD's I can get, but it is not done until
I get all the bugs checking done, as right now it is more hacking
as I go with the logic.
Is there any need for any "byte-edness" at all? Stick with a
convenient word size, make it easy to shift and mask out subfields
and forget about "bytes". You get the benefit of being able to
address more memory with fewer bits if you stick to word addressing.
The IBM marketing people used to propogate the notion that the high-
end CDC mainframes were only good for "scientific" applications
(read: "written in FORTRAN), where the S/360 architecture with its
rich memory-to-memory byte and BCD manipulation instruction
repertoire would smoke the competition in "commercial" applications
(read: "written in COBOL").
In fact, for a time, CDC had one of the fastest COBOLs on the planet,
S/360 notwithstanding. When you can do things 60 bits at a time fast
enough to keep memory busy, you don't need a fancy "commercial
instruction set" option. Seymour Cray was no idiot.
I submit that the details of any instruction set over another hardly
matters, so long as an instruction set is complete (i.e., there's no
"you can't get there from here" situation) and is executed
efficiently.
Cheers,
Chuck
15 Dec
15 Dec
12:43 a.m.
Chuck Guzis wrote:
Is there any need for any "byte-edness" at
all? Stick with a
convenient word size, make it easy to shift and mask out subfields
and forget about "bytes". You get the benefit of being able to
address more memory with fewer bits if you stick to word addressing.
BIg ENDIAN lives on my machine... :)
I submit that the details of any instruction set over
another hardly
matters, so long as an instruction set is complete (i.e., there's no
"you can't get there from here" situation) and is executed
efficiently.
One instruction computers[1]: Compliment and add, jmp if negitive
are not exactly popular for some reason... Hmmm
Cheers,
Chuck
[1] Something like that anyhow.
1:39 a.m.
On 14 Dec 2008 at 17:43, bfranchuk at jetnet.ab.ca wrote:
One instruction computers[1]: Compliment and add, jmp
if negitive
are not exactly popular for some reason... Hmmm
Make it fast enough, who cares? I kind of like move architecture,
myself. While some believe in complimenting twice, I say once is
good enough--why encourage a swelled head? :)
Cheers,
Chuck
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