7 Jul
1999
7 Jul
'99
12:13 p.m.
So I've identified and corrected one problem
with the front panel and now the address lights
and switches seem to respond correctly to EXAMINE,
EXAMINE NEXT and DEPOSIT NEXT.
For those who might be curious...
U15 (74ls04) had apparently been replaced several
times. In particular, the area around the pad for
pin 11 was rather charred. There seemed to be some
conductivity between pin 11 and one of its neighbors.
I desoldered U15 and soldered in a socket. Then cut
the trace about 1/8" from pin 11, reinserted U15
with pin 11 bent out and "air wired" pin 11 to a
convenient hole-through a little further down the
trace. Much better!
So now, on to the data lights. With no memory board
installed, I get 0xFF (all 8 data lights on) for any
address. This is correct behavior, is it not? I then
put in the INDUSTRIAL MICRO SYSTEMS 8K MEMORY BD.
Checking each 4K (0x0000, 0x1000, ..., 0xE000, 0xF000)
I still get nothing but 0xFF. Try DEPOSITing 0x00 at
each 4K, still nothing but 0xFF. On the board, J1 is
jumpered at 0 (choices being 0-7). I assume that this
is the bank number and that would make this board 8K
starting at address 0. J2 is open (I have no idea what
this means).
By the way... on the front panel, when powered up, the
PROGRAMMED OUTPUT lights are all on. Is this correct?
Thanks,
Bill
7 Jul
7 Jul
2:29 p.m.
"Bill Sudbrink" <bill(a)chipware.com> wrote:
I then
put in the INDUSTRIAL MICRO SYSTEMS 8K MEMORY BD.
Hi Bill
If this is a dynamic memory board it may not work.
None of the dynamic boards, I tried, seemed to work
from the front panel. I don't know if they do work
under normal CPU access as I didn't try it.
The output lights are at address 0FFh and the lights
go on when you write 0's and off when you write 1's.
I don't recall if they are all lit at power on or not.
I still don't know how a ls04 could have caused a
swap of your data lines??
Dwight
2:56 p.m.
If this is a dynamic memory board it may not work.
No it is 8K of 2102 static.
None of the dynamic boards, I tried, seemed to work
from the front panel.
This front panel has the DRAM modification (IMSAI number
ECN 77-0039) which apparently changes how S-100 pin 71
is interpreted.
I still don't know how a ls04 could have caused a
swap of your data lines??
No no, didn't cause the swap. The data cable _was_
backwards. Bit 7 (the high bit) was "sort of" (about
5K ohms) grounded to a neighboring pin at U15 which was
often low. This resulted in that bit almost always being
0. When the cable was backwards, you would get an 0xC2
(JNZ) instead of an 0xC3 (JMP) which would work, with the
exception of the address being reversed by the byte and
the "low" (really high) address bit always zero.
If you put the data cable in the right way, you got an
0x43 (invalid instruction) which did not put an address
on the address bus and gave the impression that random
lights were flashing on each press of the EXAMINE switch.
The system is still flakey as heck. With my limited time,
resources and knowledge it might take me a couple of years
to get it working and stable. I'm considering asking Jim
Willing what he would charge to get it put back together.
Bill
4:54 p.m.
"Bill Sudbrink" <bill(a)chipware.com> wrote:
---snip---
If this is a
dynamic memory board it may not work.
No it is 8K of 2102 static.
The system is still flakey as heck. With my limited time,
resources and knowledge it might take me a couple of years
to get it working and stable. I'm considering asking Jim
Willing what he would charge to get it put back together.
Hi Bill
You should continue on it. There was an issue with what
write signal that the RAM used. It seems like I remember
that my static boards had a switch to select -write or PWR.
One is directly from the front panel and the other is
from the processor board. This is most likely the
trouble.
Notice that the phase is inverted.
Dwight
7:54 p.m.
At 05:13 PM 07/07/1999 -0400, you wrote:
So now, on to the data lights. With no memory board
installed, I get 0xFF (all 8 data lights on) for any
address. This is correct behavior, is it not?
Yep...
I then
put in the INDUSTRIAL MICRO SYSTEMS 8K MEMORY BD.
Checking each 4K (0x0000, 0x1000, ..., 0xE000, 0xF000)
I still get nothing but 0xFF. Try DEPOSITing 0x00 at
each 4K, still nothing but 0xFF. On the board, J1 is
jumpered at 0 (choices being 0-7). I assume that this
is the bank number and that would make this board 8K
starting at address 0. J2 is open (I have no idea what
this means).
"Bank" may well be the key here. If this board is the same as most of the
Industrial Micro Boards that I've got in my collection, they are static
boards and should work just fine in an IMSAI, but there are two sets of
jumpers to set.
One sets the base memory address, and the other sets the 'Bank' number that
the board responds to. This was used in early 'bank switching' schemes to
extend memory beyond the 64k addressing limit.
There may also be a set of jumpers to set the I/O Address for the bank
control port, and to set if the board enables on power-up or not.
What all sets of jumpers does your boards have on it? If the layout is
similar, I can pull one of the boards (and or docs) down and probably give
you some more information.
-jim
---
jimw(a)computergarage.org
The Computer Garage - http://www.computergarage.org
Computer Garage Fax - (503) 646-0174
8 Jul
8 Jul
6:10 a.m.
What all sets of jumpers does your boards have on it?
If the layout is similar, I can pull one of the boards
(and or docs) down and probably give you some more
information.
OK, here's what I see:
Component side:
4 voltage regulators evenly spaced across the top.
(checked voltage on each of these... 5.00 volts according
to my digital multimeter).
Top Center:
INDUSTRIAL
MICRO
SYSTEMS
8K MEMORY BD.
Between the two right VRs (labeled VR3 and VR4):
I <micro symbol> S
C00231
Sixty-four 21L02HPC chips arranged in two blocks,
each consisting of four rows of eight chips with
pin 1 down and to the right.
Between the two blocks (also with pin 1 down and to
the right) are seven chips and two jumpers arranged
something like:
J1 7 .. SN
6 .. 74 . J2
5 .. LS .
4 .. 13
3 .. 8N
2 ..
1 ..
0 ..
RA SN
15 74
-4 LS
.7 13
KN 8N
N8 N8
T9 T9
7N 7N
74 74
LS LS
37 36
A 7P
C
J1 is presently jumpered at 0. J2 is presently open.
That's it really, nothing else of note except that there
are four components missing: CR1, CR2, CR3, CR4. Each
next to the corresponding: VR1, VR2, VR3, VR4. It looks
like they were never installed. Again, I checked the
voltages and they were 5 volts right on the money.
Thanks,
Bill
4:52 a.m.
Hi all,
At 11:10 AM 7/8/99 -0400, Bill wrote:
That's it really, nothing else of note except that
there
are four components missing: CR1, CR2, CR3, CR4. Each
next to the corresponding: VR1, VR2, VR3, VR4. It looks
like they were never installed. Again, I checked the
voltages and they were 5 volts right on the money.
Many 8K static memory boards had provision for battery backup. Some cards
used S100 pin 14 for this. These diodes were to feed the battery voltage to
the VR outputs. They are not required if you are not using a backup battery
with this card.
-Dave
9:41 a.m.
Many 8K static memory boards had provision for battery
backup.
Some cards used S100 pin 14 for this. These diodes were to feed
the battery voltage to the VR outputs. They are not required if
you are not using a backup battery with this card.
Yup! That's just how they are wired. Now, I've just put it back
in, and the behavior has changed! I still can't DEPOSIT anything,
however there does now seem to be data in the card. It's in an
interesting pattern (excuse the C syntax):
if (address == 0x0000)
data = 0xCF;
else if (address & 0x0200)
{
if (address & 0x0002)
data = 0x00;
else
data = 0xFF;
}
else
{
if (address & 0x0002)
data = 0xFF;
else
data = 0x00;
}
Do static RAMs just power up with random data or does this indicate
some kind of crossover between the address and data lines?
Thanks,
Bill
6:52 a.m.
At 02:41 PM 7/8/99 -0400, Bill wrote:
...
Yes, many static memory cards powered up with blocks, usually 2^x bytes of
data equal or approx. 0FFh or 00h.
I can understand how this would happen in byte wide rams like 6116 and
later where the bits in each byte could be physically related, but it also
happens in bit wide rams such as 2102's.
I would follow up on the posts about "Mwrite" signals.
Mwrite = S100 pin 68, active high,
pWR (processor write) = S100 pin 77, active low.
-Dave
Many 8K static
memory boards had provision for battery backup.
Some cards used S100 pin 14 for this. These diodes were to feed
the battery voltage to the VR outputs. They are not required if
you are not using a backup battery with this card.
Yup! That's just how they are wired. Now, I've just put it back
in, and the behavior has changed! I still can't DEPOSIT anything,
however there does now seem to be data in the card. It's in an
interesting pattern (excuse the C syntax):
if (address == 0x0000)
data = 0xCF;
11:41 a.m.
I would follow up on the posts about
"Mwrite" signals.
Mwrite = S100 pin 68, active high,
pWR (processor write) = S100 pin 77, active low.
OK. S-100 pins:
On the memory card:
Pin 68 goes to the N74LS37A pin 9 (seems to be an input pin).
Pin 77 has no connection, right at the card edge.
It does not go to any jumper or option pad, etc.
On the front panel:
Pin 68 goes to U24 (8T97) pin 5 (an output pin). I
have not verified the logic on the other side
of that pin (which would be pin 4).
Pin 77 goes to U5 (8212) pin 2 which seems to control
the latch for the user data lights. It also
seems to go into the DEPOSIT logic.
On the MPU-A:
Pin 68 has no connection, right at the card edge.
Pin 77 goes to an 8T97 pin 9 (an output pin).
Now that I look at it this way, this is VERY WEIRD!
Maybe very bad? Does this mean that the CPU can not
write to this memory card? Does the front panel
arbitrate pin 68 for the CPU?
Thanks,
Bill
9:11 a.m.
Hi Bill and all,
At 04:41 PM 7/8/99 -0400, Bill wrote:
OK. S-100 pins:
On the memory card:
Pin 68 goes to the N74LS37A pin 9 (seems to be an input pin).
Pin 77 has no connection, right at the card edge.
It does not go to any jumper or option pad, etc.
OK, so it expects Mwrite.
Some cards had a jumper so you could select
either one.
On the front panel:
Pin 68 goes to U24 (8T97) pin 5 (an output pin). I
have not verified the logic on the other side
of that pin (which would be pin 4).
Pin 77 goes to U5 (8212) pin 2 which seems to control
the latch for the user data lights. It also
seems to go into the DEPOSIT logic.
Yes, pin 77 also goes to U25, pin 1 (7400) where it is combined with /deposit.
It is then combined with Sout in another gate of U25 and outputted by U24
which is always enabled.
On the MPU-A:
Pin 68 has no connection, right at the card edge.
Pin 77 goes to an 8T97 pin 9 (an output pin).
Now that I look at it this way, this is VERY WEIRD!
Maybe very bad? Does this mean that the CPU can not
write to this memory card? Does the front panel
arbitrate pin 68 for the CPU?
Yes, you write to memory with deposit or (processor write & not output)
It should work if all this logic is OK.
-Dave
9147
days inactive
9148
days old
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