From: Philipp Hachtmann <hachti at hachti.de> --- Philipp, I hope you will permit me to answer criticism. I think that if we keep it cordial and constructive, it will serve the useful purpose of answering concerns about Omnibus interfacing. I can show that, in fact, the interface approach being used is completely compatible with DEC Omnibus interface practice. From: Eric Smith <spacewar at gmail.com>: --- Hi Eric, As I pointed out before, I didn't claim in the article that the receivers meet "Omnibus specifications", only that I judged it to be close enough. (The transmitters easily exceed DEC practice.) I apologize if the way I originally presented it was confusing. One of the problems with establishing compatibility with Omnibus specifications is that no comprehensive Omnibus specs have turned up so far. Instead, we have to look at actual DEC design practice. Since you raised concerns about it, I have rewritten the section to clarify the matter. In doing so, I did additional research which revealed that DEC used various ordinary TTL gates as Omnibus receivers on many occasions. There is a list of twelve citations, involving 58 Omnibus connections, which documents this practice. TTL gates used include 74H87, 74H04, 74153, 7404, 7412, 7439, 7410, 7430, 7474, and 74H11. These were employed for timing signals, control signals and for data buses. This list is by no means comprehensive, since I only spent a short time searching schematics. No doubt, we could find many other instances. You can see the full table at: http://tronola.com/html/ram_for_pdp-8e.html#Secret The conclusion from this table is that DEC certainly regarded standard TTL input specs as adequate for an Omnibus receiver. Moreover, the specs on the Omnibus interfaces of the 32K RAM board are as good or better than the cited DEC instances. Since quite a few of these instances involve critical signals of CPU cards, we can say that virtually all PDP-8/e, f and m systems have receivers with standard TTL interface characteristics. Thus, there is no reason to suspect that there will be any limitations in using this design, relative to existing DEC hardware. I appreciate your giving me an opportunity to clarify things and to hopefully lay to rest, any concerns about the interfaces. Steve Lafferty