On Tue, Jan 20, 2009 at 5:26 PM, Doug Jackson <doug at stillhq.com> wrote: Nice. OK. I think the problem is that you chose $8000 (A15). ISTR the system checks $8000 for some sort of signature and thinks that there's ROM there and jumps to it. You have to have RAM at $1000 for variables, $1100 for BASIC instructions in order for the onboard Tiny BASIC to work. For a simple system, you need to not have anything show up at $8000. I believe that is correct. NRDS is not asserted when addresses below $1000 (i.e. - on the chip) are invoked. I think you said elsewhere that you have the resistors on the correct data lines for the ROM code to pick up a baud rate value (the official address is, I think, at $FFC0 or close by - I think I've posted the details on the list before). I have a couple of INS8073 systems... one is the RB5X robot CPU board - it has discrete TTL decoding of most of the address space with '138s and '154s. It has RAM starting at $1000 and going up to around $3000 (8K onboard, with more possible with an expansion slot board). It has a ROM socket on the control panel (for ROM carriers) at $8000, and three 8255s as the primary I/O. I don't have the schematics in front of me, so I'm working from memory, but the details are published. The other 8073 system I have is an "MC-1N" SBC board that I've also posted about on this list. It is much simpler - the CPU, one 8255, a National Semi clock-calendar chip, a 2K SRAM, a socket for an optional ROM, level shifters for serial, and a 32x8 O.C. PROM (w/external pullups) for mapping the address space. It's much simpler - they piped A15-A11 of the CPU to A4-A0 of the ROM. When a device is supposed to be selected, there's a zero in the ROM map (low-true) that matches the address arrangement. There's selects for the 8255, the clock, the virtual baud-rate register (jumpers at the edge of the board), the ROM, the onboard, RAM, and three nonexistent 2K SRAMs (but one could add them without reprogramming the PROM). It really isn't overly complicated, so my guess is that either the system really didn't like you using A15, or there's something about the way you implemented the baud-rate register that the ROM code isn't recognizing. With an 8K SRAM, try A12 or A13. Also, check the states of the databus with the CPU removed to ensure that the "blank" value makes sense if the ROM code reads it and tries to decode that as serial speed jumper settings. I don't recall what the exact values are, but I do have docs for the MC-1N on a webpage, and those values should be in the INS8073 datasheets. ISTR the acceptable values are 300bps, 1200bps, and 4800bps, with a note that 4800bps isn't as reliable as the slower speeds. -ethan

Interesting, it lasted all of 8 hours. I have a couple of Psion II kits myself. I guess I won't use Buy it Now. Paxton -- Paxton Hoag Astoria, OR USA