On 2015-Jan-24, at 11:59 AM, Noel Chiappa wrote: If I'm following your observations adequately and starting from the assumption the observations you present are sufficient, it is being implied that after the memory is accessed some failure results in the state of the 3-point circuit latching up. I take it that the other wire-OR'd bit-lines return to +2V after the memory access. Given: - There are two banks (upper & lower) of memory chips wire-OR'd together. - nCAS of the mem chips acts as the tri-state control for the chip data output. - When a memory location is accessed, nCAS for one of the upper or lower bank of mem chips will be sent low, enabling data output to the 373 latch inputs. - The 373 latch control will be strobed to latch the data into the 373, while nCAS is low. (Are they 4116 memory chips in use?) Assuming you have ODT or a front panel available where you have atomic control over memory accesses ..., a means to isolate which of the 3 points (ICs/pins) is the problem might (not guaranteed) be: - Clear the circuit state to +2V state. - Access the low bank of memory. - Note the circuit state. - Clear the circuit state to +2V state. - Access the high bank of memory. - Note the circuit state. If the state after both accesses is +5 (faulty) then it suggests the 373 is the failure point. If the state is only faulty after one of the accesses it suggests the according mem chip is the failure point. You might want to play with writing 0 or 1 into the location prior to the read, it's difficult to be exhaustive at this distance for all the possible test/failure scenarios, but you get the idea: distinguish the accesses to the upper and lower bank to try to isolate when the circuit enters the faulty state, and see whether it's common to both banks or only one. You might also try scoping the various nRAS, nCAS, 373 strobe inputs along with the faulty circuit to see if you can discern time coincidence between activity on one of those inputs and entering the fault state.