Having read through the discussion, I sat down and sketched out some "flip chip" type designs. Units of logic that could be wired together to create the CPU. When I did this I was striving for a fairly universal design so, as John put it, we could have a whole bunch made and get the benefit of volume manufacturing. Well, not too suprisingly (ask the right question, get the same answer) I was about halfway through my sketched out design when I realized I was duplicating something I had seen in a databook, a Xilinx databook to be precise. The flip chips are the "CLB"s (Complex Logic Blocks) of your standard gate array design. The backplane is the interconnects. The problem is reduced to the complexity of implementing the FPGA architecture and then having the tools send out wrap lists rather than routing configs :-) --Chuck