Well . . . If I were in your position, and I am, sort-of, I'd have my 'scope out and be looking at the bus cycles and the memory cycles. If the DMAC on the FDC generates cycles similar to those generated by the CPU, then you're in good shape, since you then have only to make the DRAM board work with one and it will probably work with both. It's been a long time since I looked at S-100 hardware and I'm just now starting to put some boxes up in order to verify functionality of some of the dozens and dozens of boards sitting around. Since I have several of each, in many cases, I just need to figure out an appropriate way to test each one and then go through the set. For debug purposes, I may generate a PROM for each debug function I need. Firs, however, I have to haul that big Integrand box with the 8" Winchester out onto the patio and set a terninal on top of it. Even if you don't intend to use PROMs in your final device, I'd certainly recommend you build a few PROMS which make the processor do rudimentary things and perhaps which make the DMAC do the same things. You then have simple tools with which to troubleshoot your memory interfaces. After reading about the problems you're having, I think I'll fetch the 1240 LA out onto the patio as well. Dick -----Original Message----- From: Dwight Elvey <elvey(a)hal.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Tuesday, June 01, 1999 6:43 PM Subject: Re[4]: More Bringing up a CPM