Yes, increasing the amount of memory by 1/8 increases the likelihood of failure by 1/8. The inclination to bury one's head and ignore the potential for memory or bus failure comes from the competition for price advantage on the personal computer market, though. The argument I've heard is "if MAC'c can live with it, so can PC's" which may not be true, but appears to be true enough for the typical user. Once such a memory failure is detected, there's nothing you can do about it except endeavor NOT to save the data which may be corrupted and become aware of the problem. I see memory parity errors (most of the PC's here use parity or single bit error correction) about twice a year. Normally it's when a new box is being brought up and memories aren't seated right or something on that order. I don't know what that says about the memory systems of today. It's been a few years, but I always preferred single-bit correction over parity in sizeable memory arrays. I designed one fairly large buffer memory for Honeywell, which had 72-bit-wide memory, 64 MB deep, which was quite a bit for that time (1991) with single bit correction only to have the manager tell me it was not needed. "Whom are we helping with this added expense?" was his position. I pointed out that it would make memory problems a depot or even field repair whereas it would be a return-to-factory otherwise. He insisted, though. The software lead and I agreed we'd base our memory check on parity, which still allowed for isolation of the faulty SIMM. Since this was not a main system memory but just a data buffer, it didn't matter that it ws defective and firmware could rigorously isolate the faulty device. I'm not sure what you're saying about the relative value of the extra bit of memory versus the risk of promulgating a transient error into infinity by recording it as though it were correct, Ethan. You seem to suggest that it would have been better not to have had the 60-cent memory part in place rather than to find and repair it once its failure was detected by parity circuitry. I doubt you believe that, however. It is true that the addition of parity circuitry means that there is an elevated likelihood of failure proportinal to the increased memory size. It is also true that parity checking circuitry requires time to work, and can, itself, fail as well. Increased circuit complexity does increase the statistical probability of failure. ECC circuitry doesn't decrease the probability of memory failure. It does decrease the amount of down-time resulting from it, and it avoids the data loss and down-time associated with single-bit transient failures, which are more common than hard failures. I guess it's like automobile insurance. If you have assets you need to protect, you buy it. If you haven't you don't. My assessment is that Apple started with the assumption that you don't. Dick -----Original Message----- From: Ethan Dicks <ethan_dicks(a)yahoo.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Friday, April 09, 1999 6:10 AM Subject: Parity (was Re: stepping machanism of Apple Disk ][ drive) the mind or corrected 72-pin but butt. even because that the an and company correct