26 Jul
2005
26 Jul
'05
3:03 a.m.
Anyone know about anything similar to this?
http://www.datexeuropa.com/emulatoren/DTX300-ENG.pdf
Mostly interested in something I could build. Probably couldn't even afford
the shipping on a unit like this.
Just dreading the day I finally run out of ST-506 hard drives.
Kelly
26 Jul
26 Jul
3:42 p.m.
On Mon, 2005-07-25 at 22:03 -0400, Kelly Leavitt wrote:
Anyone know about anything similar to this?
http://www.datexeuropa.com/emulatoren/DTX300-ENG.pdf
Mostly interested in something I could build. Probably couldn't even afford
the shipping on a unit like this.
I'm not sure how complex such a box would be. I *think* an ST506-
interface drive looks pretty much like a big floppy, just with more
heads. Far as I know, it doesn't do anything intelligent on the drive
itself, just responds to head select / step commands from the controller
and reads or writes data.
The bit I don't know is the nature of the data signal at the interface -
it uses +/- signal lines for both read and write data. I'm not sure if
that's an analogue signal or a digital one.
I could imagine a device containing a pile of non-volatile memory in a
row/column arrangement. There'd be a free-running counter to address the
memory row and simulate the rotation of the drive (this would also drive
the index line when at address 0). Then there'd be a second counter
linked to the memory column and controlled by the step line on the
interface, in order to simulate a drive track; this would also drive the
track 0 line when at address 0.
OK, that's only simulating a single head; but it just scales up with
more memory planes to simulate more platter surfaces.
I *think* that would be it; the controller writes the necessary bit
patterns when doing a LLF of the drive to mark out sector boundaries, so
I don't think there's a need to handle anything complex in the virtual
drive. I believe an ST506 drive's purely a data store/replay device and
it knows nothing of the actual data stored on it - most of the circuirty
on board is presumably just motor control and head amplifiers / filters.
I'd have no idea how to properly design something on a PCB that'd work
though at the sort of necessary speeds without noise problems! But I
think *in theory* it's probably not a difficult thing to design, and
just needs a good electronic engineer to do the PCB work. Arguments
welcome though :-)
Yes we've been here before on this list - I think that was working out
how to replace a ST506 drive with IDE though (which of course does know
about sectors and stuff) - hopefully driving a pile of NVRAM as a linear
sequence of bits is a lot easier.
Just dreading the day I finally run out of ST-506
hard drives.
I'm got a few stockpiled at the museum, both for ourselves and for if
anyone else needs one in an emergency - people locally seem to dispose
of them quite often, so I just save what I can. Of course the majority
of them are probably in a non-working condition anyway!
cheers
Jules
7:01 p.m.
I'm not sure how complex such a box would be. I
*think* an ST506-
interface drive looks pretty much like a big floppy, just with more
Correct. Don't uou have at least one ST506/ST412-interfaced drive schematic?
heads. Far as I know, it doesn't do anything
intelligent on the drive
itself, just responds to head select / step commands from the controller
and reads or writes data.
The bit I don't know is the nature of the data signal at the interface -
it uses +/- signal lines for both read and write data. I'm not sure if
that's an analogue signal or a digital one.
It's differentical digital. The line drivers are 26LS31s, the receivers
26LS32s (at least normally). It's much the same as the floppy read data /
write data line, just faster.
The problem is that although the signal is digital in amplitude (2
states), it's analogue in time. There are restrictions (both minimum and
maximum) on the time between data pulses, but apart from that you can
essentailly do what you like. The drive does not impose any restrictions
on the data format, the format of the sector header, etc. You could write
18 bit words if you wanted to.
I could imagine a device containing a pile of non-volatile memory in a
row/column arrangement. There'd be a free-running counter to address the
memory row and simulate the rotation of the drive (this would also drive
the index line when at address 0). Then there'd be a second counter
linked to the memory column and controlled by the step line on the
interface, in order to simulate a drive track; this would also drive the
track 0 line when at address 0.
OK, that's only simulating a single head; but it just scales up with
more memory planes to simulate more platter surfaces.
You need to sample and replay at about 10 times the data rate. That's
50MHz. Do-able, but a bit harder than you imply. You need to keep on
replaying a given track's data, and do the right thing (I nearly said
write thing :-() if write gate gets asserted. Remember the interface is
bit serial, preesumably your memory is at least 8 bits wide, you may well
have to start writing in the middle of a memory word.
As I said, it's not that difficult, just a bit harder than you may have
first thoguth.
-tony
9:11 p.m.
On Tue, 2005-07-26 at 19:01 +0100, Tony Duell wrote:
Nope, unfortunately not :-( I've got various manuals for bridge boards,
which of course have the connector pin-outs in (and give some of the
theory), but nothing for a complete hard drive (I suppose I'mactually
surprised such schematics ever escaped the drive manufactuers to be
honest, as presumably ST506/412 units were never supposed to be field
servicable?)
Aha, good.
I'm not
sure how complex such a box would be. I *think* an ST506-
interface drive looks pretty much like a big floppy, just with more
Correct. Don't uou have at least one ST506/ST412-interfaced drive schematic? heads. Far as
I know, it doesn't do anything intelligent on the drive
itself, just responds to head select / step commands from the controller
and reads or writes data.
The bit I don't know is the nature of the data signal at the interface -
it uses +/- signal lines for both read and write data. I'm not sure if
that's an analogue signal or a digital one.
It's differentical digital. The line drivers are 26LS31s, the receivers
26LS32s (at least normally). It's much the same as the floppy read data /
write data line, just faster. The problem is that although the signal is digital in
amplitude (2
states), it's analogue in time. There are restrictions (both minimum and
maximum) on the time between data pulses, but apart from that you can
essentailly do what you like. The drive does not impose any restrictions
on the data format, the format of the sector header, etc. You could write
18 bit words if you wanted to.
I was googling for the proper spec earlier but so far haven't been able
to find it :-( (presumably because it's not something hobbyists ever
really messed with)
You need to sample and replay at about 10 times the
data rate. That's
50MHz. Do-able, but a bit harder than you imply.
If 8x is enough then that could make the logic easy I suppose, with 8
bit wide memory (some sort of shift register for writes, only clock data
into memory on every 8th clock pulse say).
Whether something like compact flash will handle that data rate
though... perhaps it requires buffering at the track level and only
writing to flash on track changes (which the controller presumably
expects to be quite slow). It gets a bit complicated at that point!
cheers
Jules
9:02 p.m.
Correct.
Don't uou have at least one ST506/ST412-interfaced drive schematic?
Nope, unfortunately not :-( I've got various manuals for bridge boards,
which of course have the connector pin-outs in (and give some of the
theory), but nothing for a complete hard drive (I suppose I'mactually
surprised such schematics ever escaped the drive manufactuers to be
honest, as presumably ST506/412 units were never supposed to be field
servicable?) 
28 Jul
28 Jul
1:34 a.m.
On Tue, 26 Jul 2005 21:02:47 +0100 (BST)
ard at p850ug1.demon.co.uk (Tony Duell) wrote:
THe HDAs were not field-repairable, but the PCBs certainly were/are.
The IBM PC series TechResf contain schematics of some such drives
(which ones depends on exactly which version fo the TechRef amd which
updates you have). I've traced out a couple more. In general these
drives are not particularly complicated, although there may well be
ASICs for things like head switching, motor control, etc.
At one point I grabbed a copy, I don't know where I got it, but think it
was from a Tandy 4000 Technical Reference Manual, of a Technical
Reference the ST-225 (the old classic 20 meg ST-506 drive that EVERYBODY
had back then.) I believe it has schematic diagrams. The bad thing is
that it's in a file cabinet behind a BIG pile of gear right now.
Correct. Don't uou have at least one
ST506/ST412-interfaced drive
schematic?
Nope, unfortunately not :-( I've got various manuals for bridge
boards, which of course have the connector pin-outs in (and give
some of the theory), but nothing for a complete hard drive (I
suppose I'mactually surprised such schematics ever escaped the drive
manufactuers to be honest, as presumably ST506/412 units were never
supposed to be field servicable?) 
26 Jul
26 Jul
9:15 p.m.
At 03:11 PM 7/26/2005, Jules Richardson wrote:
On Tue, 2005-07-26 at 19:01 +0100, Tony Duell wrote:
schematic?
the IBM XT Technical Reference manual has schematics for the 10meg
hard drive that was in the XT
I'm
not sure how complex such a box would be. I *think* an ST506-
interface drive looks pretty much like a big floppy, just with more
Correct. Don't uou have at least one ST506/ST412-interfaced drive 
28 Jul
28 Jul
7:55 p.m.
On 7/26/05, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
Remember the interface is
bit serial, preesumably your memory is at least 8 bits wide, you may well
have to start writing in the middle of a memory word.
Are you sure about that 50 MHz? I would have guessed 10 MHz would be
fast enough.
Um, wouldn't you use each bit in a word as a different head rather
than than address bits withing a word? It's not like you can't
perform an SRAM read+write cycle in 20 ns, although direct to [S]DRAM
might be a bit more challenging. So in terms of 50 MHz sampling,
you're talking 1 Mbit per head of fast memory for cylinder cache (you
might as well choose a multiple of 8 heads), 1Mbit per head per
cylinder of slow non-volatile memory for storage, and a PIC to
transfer between the two (handle the "stepping") and a FPGA to hold
the logic (a resettable 50 MHz, 20 bit counter tristated to the cache
address bus and the read/write logic) So a 20 MB drive (8*640*17) is
1 MByte of fast memory, and 640 MB CF card. If 10 MHz is fast enough
you can reduce those memory requirements by a factor of 5.
As I said, it's not that difficult, just a bit
harder than you may have
first thoguth.
Sounds like fun. :) Wish I had the time...
Eric
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