hardware multiply/divide functionality in CPUs - test-drb@ccmp.vtda.org

9 Mar 2011

...
  background: I'm revisiting a homebrew microcoded
CPU that I started 
 thinking about a few years ago (with the intention of making it 
 predominantly from LS-TTL if I can get enough parts together). I hadn't 
 considered hardware multiply or divide before (the intention was just to 
 have library routines in software), but if it was relatively common on 
 systems between the mid-70s and early-80s then maybe I'll include 
 something. Simple shift-add multiply with unsigned integers is simple 
 enough, but I'm thinking that if I do it at all it'd be nice for it to work 
 with signed integers, too, so I've got some head-scratching to do :-) 
As to "common", if your CPU starts looking like a 68000 or 8086, then
you'll
probably have both signed and unsigned multiply and divide.

(I think the original x86 had some instructions to assist with BCD multiply?)

68000 or 80x86 hardly seem like clever minimal instruction sets today... and
for a long time those implementing CPU designs have tended towards RISC.

e.g. PA-RISC was in production from 1986 through 2008, was a high performance
micro, and had no hardware multiply. If you're looking for a good model for
implementing in 74xx series logic, keep in mind that in 1986, HP was selling their
new workstation, the HP 9000 840, which had its CPU largely implemented in 74F
series logic (I think there were some PAL's etc. but my memory fades).

IMHO unsigned multiply will usually be most appropriate for the bit twiddling
a micro has to do. BUT... if you're gonna do Fortran benchmarks, you
probably want signed multiply. (This is a sore point when it comes to
implementing bit-twiddling multiplies in Fortran. Understandable because
Fortran was designed around ones-complement processors.)

Tim.