Concerning daisy chained jumpers: priority jumpers that are daisy chained. I believe this is how it works: There is one interrupt line going to the CPU from all devices, so the daisy chain system is used to define the interrupt priority when 2 or more devices are interrupting at the same time by only allowing the device electrically closes, in the daisy chain, to the CPU, to be allowed to answer the "interrupt acknowledge" CPU instruction by ANDing the daisy chain line with the device's interrupt line and using other logic to disable the daisy chain line from continuing on to the next device. The acknowledging device would then be able to put its device code (ID) on the buss for the CPU to read. Of course, in other situations, when only one interrupt is activate at a time, interrupt priority can be controlled in SW by disabling specific or all device interrupts and by deciding whether or not to service an interrupting device. I don't remember if the data channels had a special dedicated interrupt line to signal when they were finished with a data tranfer or if they were treated as just another device. I don't have my DG books handy (in storage) to be able to find exactly what title covers this subject. ----- Original Message ----- From: "Jay West" <jwest at classiccmp.org> To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org> Sent: Saturday, August 28, 2010 11:23 PM Subject: dg 1200 queries After some very minor cleanup and front panel fixing, the DG1230 seems to spring to life. I can deposit and examine different values from all four cpu registers, as well as small random ranges of memory. I've been skimming some of the DG docs I have, but I am coming up short on knowledge on a few points and was wondering if someone could shed light on any of these items or better yet, direct me to the appropriate manual that I can't seem to find. 1) In DEC & HP documentation, I can find a fair number of "front panel dittys" to perform basic tests in the absence of I/O devices. I can find no such short programs for the DG1200. Before I attach an I/O device (CRT, Cassette, or paper tape) I'd sure like to feel more confident that the cpu is on fairly solid ground. Unless someone knows of some docs on short front panel test programs, I'll just write a few short "copy range of memory from A to B, etc." programs myself and hand assemble them. 2) At the bottom of the backlane are several small pin connectors - P5, P6, P7, P8, and P9. Going from memory, but they are something like 2 rows of about 10 pins per row for each P connector. I can't seem to find where these are documented. Can someone point me to the right manual? They don't even show up on the backplane diagrams I have. 3) On most of my DG12xx cpu's, the backplanes don't have extra wiring, other than what is obviously going to a device. But on this one, Pin 10 of backplane connectors 2 through 12 is daisychained. I believe the signal is "VINH". I can't seem to find documentation on this. I'm guessing it has to do with allowing (or disallowing) memory cards in slots other than slot 2, but I'd like some better understanding as to when and when not this jumper set should be present. 4) Again, on most of my DG12xx boxes, the backplane has nothing other than I/O connections. But on this one, pin 96 (intp in) slot five is wrapped to pin 95 slot 16 (intp out). Likewise pin 94 (dhcp in) is wrapped to pin 93 slot 16 (dhcp out). I do have some idea what this is for, but I'd like a better understanding as to when and when not this jumper should be present. This has got to be documented/explained somewhere, but I sure can't find a discussion of it. Thoughts? I'm guessing this jumper is only required to get DHCP to the upper I/O card section on the "jumbo" version? Thanks in advance for any thoughts! Jay