The WD9000 Pascal Microengine main box does not include floppy drives. It can support up to four floppy drives, which can be either 8-inch (500 kbps transfer rate), or 5.25-inch (250 kbps transfer rate), as selected by a DIP switch setting on the WD900 board. Unfortunately the DIP switch directly controls the clock rate into the 1793 FDC chip, so it is not possible to mix 250 kbps and 500 kbps drives. However, it should be possible to mix 8-inch drives with high-density 5.25 inch or 3.5 inch drives that use the 500 Kbps transfer rate. The floppy connector on the back of the WD9000 box (and the WD900 board) uses a DC37S connector, and the pinout seems to be unique to the Pascal Microengine. My Microengines did not come with the floppy drives or cabling. I've designed a simple adapter PCB, and just got the first boards back from PCBWay today. I haven't yet finished assembling one because I screwed up ordering on some of the components and connectors. Photos: https://www.flickr.com/photos/22368471 at N04/albums/72157660580290148 The WD900 board uses an FD1791 double-density floppy controller. It appears that the main board may have been originally intended for the FD1771 single-density controller, as the board revs I've seen don't have a suitable double-density data separator built in. On one of my units, the FD1791 is on a daughterboard with a typical analog data separator design using the WD1691 floppy support logic and a 74LS629 VCO. My other board has the FD1791 on the main board, but has some significant rework to install an SMC FDC9216B digital data separator chip in place of one of the TTL chips originally used by the main board design. I've seen other WD900 boards with the FDC9216B modification, so I think this was rework done at manufacturing time, rather than a field change. One aspect of the floppy controller design seems a bit unusual. The WD controllers have a HLD output used to tell the floppy drive to load the head, and an HLT input (Head Load Timing) to indicate that the head is loaded. After the controller asserts HLD, it waits for HLT to go true before proceeding with read, write, or format operations. A typical 8-inch drive takes 35 ms to load the head, and maybe a few more for head settling. A common way to wire the controller is to use an external one-shot triggered by HLD, with its output wired to HLT, and adjusted for a time delay a little longer than the drive requires for loading the head. 8-inch drives typically can either be jumpered to use a dedicated head load control line on the interface to control the head load solenoid, or to automatically load and unload the head as the drive select signal is asserted and deasserted. Normal 8-inch drives have the head load solenoid to do what was previously described, and run the spindle motor either all the time, or whenever a disk is inserted and the door closed. 5.25-inch drives, and some later 8-inch drives such as the Tandon TM848, do away with the head load solenoid and instead are intended to operate with the spindle motor active only when the drive is selected, or when a motor control signal is active. As such, they don't require any head load time, but instead require a motor startup time that is even longer; the slowest drives require about a second for spinup. With a WD controller, this is also sometimes accomodated by using the one-shot between HLD and HLT. Some WD-based controller designs, such as those in the TRS-80 Model I, III, and 4, are only intended for 5.25-inch drives (or the 8-inch drives that use motor control and no head load solenoid), and tie the READY signal from the drive to the HLT input of the FDC. The WD900 board tries to acommodate these variations by bringing the HLT signal to its DC37S connector, for the system integrator to wire up as desired. The only complete Pascal Microengine system I've seen up close in recent history had a hand-wired drive cable to 8-inch drives, with the HLT signal simply tied to a +5V pin on the same connector. The net effect of that is that the FD1791 asserts HLD, delays 15ms if the h bit of the command is 1, and does not delay any further. Unless the drive can actually load its head that quickly, this doesn't seem ideal, but I suppose it works because the FDC won't be able to read a valid sector address field until the head is loaded. For a write operation, I'd worry that the head might not have fully settled by the time the actual write begins, possibly leading to unreliable writes. To support proper head load or motor spinup timing, I put an optional PIC microcontroller and DIP switch on the adapter, to act as a digital delay between HLD and HLT, with sixteen switch-selectable delays. The drive select lines are wired to PIC inputs, so if desired, firmware could actually use different delays for different drive selects, if you mix drives with different head load timing requirements. I haven't yet written any PIC code for it. The board should basically work as described above with HLT jumpered to +5V, without the PIC and related components installed. The adapter has both a 50-pin connector for 8-inch drives, and a 34-pin connector for 5.25-inch or 3.5-inch drives. It is intended for one connector or the other to be used, but not both. Even if you use a combination of drives that all use the 500 kbps transfer rate, having them cabled separately to the two connectors could result in termination problems. Naturally, only hours after ordering the PCBs I thought of improvements that I'd like to make to the design, but I don't anticipate that there will be a second run of boards. I don't presently have any bootable disk for the Pascal Microengine, so I'm not yet able to test the adapter. However, if anyone else needs such a thing, I have a small number of bare boards that can be made available inexpensively. (I don't have time to assemble boards other than for myself.) If there's any interest, I'll publish the Eagle design files, gerber and excellon files, a PDF of the schematic, and source and object code for the PIC firmware. The firmware will be GPLv3 licensed, and the other design files with be under a Creative Commons license, probably CC BY-SA 4.0.