-----Oorspronkelijk bericht----- From: Eric Smith Sent: Sunday, January 31, 2016 1:16 AM To: General Discussion: On-Topic and Off-Topic Posts Subject: Re: PDP-11/03, LSI-11 KEV11-C CIS option On Sat, Jan 30, 2016 at 2:32 PM, Henk Gooijen <henk.gooijen at hotmail.com> wrote: Just looking for the CIS chip(s), and just to borrow long enough to dump the microcode. -------- OK, if nobody in the USA steps up, I will check where I have stored that little box. At least, I am pretty sure I have that chip. I can do that this week. Insured shipping would not cost much is it is tiny enough to be shipped in a "bubble envelop". - Henk

On Sun, 31 Jan 2016, Pete Lancashire wrote: Seconded. The machines the USPS uses for automated sorting of mail are not gentle on parcels. That said, even a box isn't foolproof, I had one small box containing 2GB registered ECC DIMMs packed in clamshells arrive that had clearly been run over by a forklift (none of the memory modules survived). I would also strongly advise anyone who uses printed shipping labels with barcodes to always use a box or mailer large enough for the label to fully fit flat on one side. If you wrap a label around a parcel, the automated label and barcode scanners in the processing machines cannot read them and those parcels tend to get delayed, sometimes for a significant amount of time (the record so far for stuff sent to me with an improperly applied label is a little over 3 months). The absolute worst thing you can do is wrap a label around a round tube horizontally...the barcode readers can't read it and the OCR scanners can't read the address. Such parcels end up having to be sorted by hand.

On Sun, Jan 31, 2016 at 2:24 AM, Henk Gooijen <henk.gooijen at hotmail.com> wrote: Hi Henk, I think what you have is probably the KEF11-B CIS option for the F11 (11/23 and 11/24). If you find it, please let me know what the markings on the hybrid and the chip carriers are, and/or take a photo. As I noted in a reply to John Wilson, I don't think we can electrically dump the KEF11-B chips. If what you have is a KEF11-B, unless you're willing to sacrifice it (for science!) or sell it, there's no reason to ship it out. Best regards, Eric

On Sun, Jan 31, 2016 at 11:38 AM, John Wilson <wilson at dbit.com> wrote: I think the KEV11-C is not full CIS, but rather a subset. It's usually described as DIBOL Instruction Set (DIS). There are two diagnostics for DIS; VKAI?? is for move and string instructions (MOVC, MOVRC, CMPC, LOCC, SKP, SCANC, SPANC), and VKAJ?? is for decimal instructions (ADDN, SUBN, CMPN, CVTNL). DIS was standard in some of the D3xx commercial-oriented LSI-11 systems, such as the D324. The KD11-P and KD11-Q processors are the M7264-BB and M7264-YB, respectively, with the KEV11-C DIS preinstalled. It's not possible to use DIS together with the KEV11-A EIS/FIS (or KEV11-B EIS) options, due both to limited number of MICROM sockets, and that the base instruction set and DIS together take up the entire microcode address space. However, the LSI-11 Systems Service Manual Volume 3 (Jan. 85) states that the VKAB?? EIS diagnostic will work with the KEV11-C, so presumably KEV11-C includes both DIS and EIS (but not FIS). My understanding is that the KEV11-C option consists of two non-hybrid MICROMs, 23-004B5 and 23-005B5, and is used with a 40-pin hybrid containing the two MICROMs of the base instruction set. The hybrid is 23-001B6, 23-002B6, or 23-003B6; I don't know what differences there are between the three hybrid part numbers, but they're described as being for M7264 ECO 10, ECO 12, and ECO 16, respectively. I've got bad news for you. The control chips of the F11 chipset aren't just ROMs; they include the control sequencer (one per control chip). Unless there's an undocumented test mode, it's not possible to dump the full microcode word, since only part of it is output to pins, and it's not possible to dump the contents purely sequentially. I think it will be necessary to dump them optically, which of course requires the chip carriers to be delidded. While this is not necessarily destructive, it can't be 100% guaranteed not to damage the chips, and even if it doesn't, the future reliability of them may be diminished. On the other hand, as you say, if we could dump the KEF11-B CIS control chips (optically or otherwise), we could build a replacement daughtercard that emulates KEF11-B, and then anyone that wanted to have CIS on their 11/23 or 11/24 would have a relatively low-cost option to do so. I'd really like to get the F11 base instruction set control (part of the DCF11 hybrid) and the KEF11-B CIS (six chip hybrid spanning two 40-pin DIP sockets) to be dumped in this way, but only if someone is willing to sacrifice them. Given that the KEF11-B is fairly uncommon, I'm not holding my breath...

On Sun, Jan 31, 2016 at 10:24 PM, John Wilson <wilson at dbit.com> wrote: The MCP1600 chipset used in the LSI-11, WD16 (Alpha Micro AM100), and WD9000 Pascal Microengine uses microcode ROMs that really are just ROMs, so I was able to read them electrically. The trick with those is that the control chip (CP1621 for LSI-11, CP1661 for WD16, CP2161 for Pascal Microengine) contain two PLAs that can cause microcode jumps based on the current microPC and the contents of the interrupt and translation registers. The contents of the microcode ROMs themselves are thus quite difficult to interpret without having the contents of the PLAs. John McMaster took photomicrographs of the CP2161 and stitched them together: https://siliconpr0n.org/map/wd/cp2161/mz_mit20x/ I was able to successfully extract the contents of the translation PLAs by inspection: I processed the PLA dumps with Python scripts into two forms, one somewhat suitable to be human-readable, and one useful as input to a simulator: http://www.brouhaha.com/~eric/retrocomputing/wd/microengine/microcode/ I used the former to annotate my microcode disasssembly, and put the latter and the microcode ROM dumps into a simulator which has now successfully executed the first 30 macroinstructions (UCSD p-code instructions) from a PDQ-3 boot ROM. A CP1621 control chip from an LSI-11 has been provided to John, and once he has a stitched photomicrograph of that, I'll do the same with it. I've already disassembled the LSI-11 microcode (base, and KEV11-A EIS/FIS), so I should be able to make progress on that quickly once the control PLAs are extracted. I plan to simulate it as well. Obviously I'd want to do the delid and photomicrograph of the F11 base instruction set control chip, which is nowhere near as rare, and verify that the contents can be extracted and make sense, before doing the same to the KEF11-B. I don't have any 11/23 (or 11/24) modules on hand, or I'd be happy to sacrifice a DCF11 to do that. If anyone would care to sacrifice one...