11 May
2019
11 May
'19
4:14 p.m.
I'm building my own 8-bit CPU from TTL chips, and this caused me to think:
how were 32-bit minis built in the late 70s and early 80s? In particular,
how was the ALU built? I know about the 74181 4-bit ALU, and I know (from
reading A Soul of a New Machine) that PALs were also used.
Did companies get custom chips fabricated, or was it all off-the-shelf chips
with a few PALs sprinkled in?
Thanks, Warren
11 May
11 May
5:28 p.m.
On 05/11/2019 07:14 PM, Warren Toomey via cctalk wrote:
I'm building my own 8-bit CPU from TTL chips, and
this caused me to think:
how were 32-bit minis built in the late 70s and early 80s? In particular,
how was the ALU built? I know about the 74181 4-bit ALU, and I know (from
reading A Soul of a New Machine) that PALs were also used.
Did companies get custom chips fabricated, or was it all off-the-shelf chips
with a few PALs sprinkled in?
Thanks, Warren
Lets see the VAX 11/780 hit the street in 78 and DG followed with theirs
soon after and of course the IBM 360 was 32bit so the number can be
fairly large. Soul of a new machine was more romantic but it was of
early VAX era and the Eclipse was the result.
Reading the following woould be better as it compared and contrasts DEC
hardware and instill an idea of ISA design and then its hardware
implementation. Its a good read and free!
http://www.bitsavers.org/pdf/dec/_Books/BellComputerEngineering.pdf
Building now is more based on what you have or can get not what was used
then as most were pushing for speed vs price and the available parts
were never fast enough and cost too much.
Not all were 74181 based, Thats an early 1972 part and but 1975 it was
already getting old though useful as it evolved to 74S and 74F series.
The 82s100 and 105 series were out there and even by 1980 the AMD 2900C
series was getting long in the tooth. Mask programable gate arrays were
in the 1000 and up gate level by 1980 and growing by doubles every 6
months to a year. Don't got get programmables like PAL/GAL logic.
There was a lot of designs and even inside DEC you might see several
approaches depending on what machine and the specific date. For example
the 780, 750 and 730 used very different technology. I will not go into
those that also went the ECL {10K, 100K, 1M families] route.
Your question has to be based on a specific date window and narrow at
that as keep in mind by 1978 16bit CPUs on silicon were a fact
(Ti9900, SBP9900, F11, T11, Nova, 8086).
6:30 p.m.
On 5/11/2019 6:28 PM, allison via cctalk wrote:
Not all were 74181 based, Thats an early 1972 part and
but 1975 it was
already getting old though useful as it evolved to 74S and 74F series.
The 82s100 and 105 series were out there and even by 1980 the AMD 2900C
series was getting long in the tooth. Mask programable gate arrays were
in the 1000 and up gate level by 1980 and growing by doubles every 6
months to a year. Don't got get programmables like PAL/GAL logic.
There was a lot of designs and even inside DEC you might see several
approaches depending on what machine and the specific date. For example
the 780, 750 and 730 used very different technology. I will not go into
those that also went the ECL {10K, 100K, 1M families] route.
74181 is FAST, but I disagree with the way most computer architecture is
designed. You have a fast micro code cycle, that is out of sync with
main memory, that tries to emulate a Harvard? Memory model.
It looks fast only on paper or demo programs sadly.
The few schematics I have seen (PDP 8/11) have 74H logic hidden
inside so you can't say they are pure TTL logic.
A cpu instruction has 4 parts in general
a) getting the instruction and literal data from memory
b) calculating the the effective address
c) fetching the data from memory c) ouputing data
d) using the data d) saving to memory.
It is very hard to speed up this cycle because this has
sync to extenal memory. Memory is the bottleneck
is the true speed limit in any sytem. Add in virtual
memory and in multitasking and graphics
no wonder the PDP 8 at with TTL gives better response
time.
Ben.
PS: this message was delayed for about a minute as
background program froze the sytem.
8:28 p.m.
On 05/11/2019 09:30 PM, ben via cctalk wrote:
On 5/11/2019 6:28 PM, allison via cctalk wrote:
TTl in general is slow a ALU based on 181 is hitting the wall at 5mhz
with 12 or 32 but carry lookahead.
Not all were 74181 based, Thats an early 1972
part and but 1975 it was
already getting old though useful as it evolved to 74S and 74F series.
The 82s100 and 105 series were out there and even by 1980 the AMD 2900C
series was getting long in the tooth. Mask programable gate arrays were
in the 1000 and up gate level by 1980 and growing by doubles every 6
months to a year. Don't got get programmables like PAL/GAL logic.
There was a lot of designs and even inside DEC you might see several
approaches depending on what machine and the specific date.? For example
the 780, 750 and 730 used very different technology.? I will not go into
those that also went the ECL {10K, 100K, 1M families] route.
74181 is FAST, but I disagree with the way most computer architecture is designed. You have a fast micro code cycle, that is
out of sync with
main memory, that tries to emulate a Harvard? Memory model.
It looks fast only on paper or demo programs sadly.
The few schematics I have seen (PDP 8/11) have 74H logic hidden
inside so you can't say they are pure TTL logic.
Yes, they are mostly TTL and the typical 8efm use MSI ttl such as
7481, a bunch of them.
I'm likely one of the few that took a 8E and ran semiconductor ram then
pushed the clock up to the breaking point and you get to about 4x and
you start getting timing errors and critical path delays that mess with
the logic. However at 4X you doing a lot and decently fast but you
needs a faster generation of logic.
?A cpu instruction has 4 parts in general
?a) getting the instruction and literal data from memory
?b) calculating the the effective address
?c) fetching the data from memory? c) ouputing data
?d) using the data d) saving to memory.
Many of those things can be done in parallel.
Whoever RMW cycles on memory even with very fast memory will slow the
system as you have cycles that cannot be interrupted mostly in the
slow memory.
It is very hard to speed up this cycle because this
has
sync to extenal memory. Memory is the bottleneck
is the true speed limit in any sytem. Add in virtual
memory and in multitasking and graphics
no wonder the PDP 8 at with TTL gives better response
time.
Memory is often the bottleneck then IO especially block IO.
The response time of PDP8 was mostly due to a simple OS and nothing to
get in the way.
The name for that is system overhead and PDP-8 had little and what it
did have was written in assembler for speed and compact code as it was
also space constrained.
Allison, have the shirt.
Ben.
PS: this message was delayed for about a minute as
background program froze the sytem.
8:52 p.m.
Marketing at the time even had a catchy name for the 32-bit minicomputer:
https://en.wikipedia.org/wiki/Superminicomputer
9:12 p.m.
On 5/11/19 8:52 PM, Nigel Williams via cctalk wrote:
Marketing at the time even had a catchy name for the
32-bit minicomputer:
https://en.wikipedia.org/wiki/Superminicomputer
Personally, I preferred "the Naked Mini"
https://www.computerhistory.org/revolution/minicomputers/11/359
--Chuck
10:21 p.m.
On 5/11/19 9:52 PM, ben via cctalk wrote:
On 5/11/2019 10:12 PM, Chuck Guzis via cctalk wrote:
Maybe--it was an 8 bit mini, so not very powerful. Mostly used in what
we'd call "embedded" applications. Pre-microprocessor days.
I can remember back in the early 70s picking up some surplus PCBs with
plain 7400 (not LS) logic, including a couple of 74181 ALUs and a 74199
shift register, both in 0.600" 24 pin DIPS--and lots of SSI TTL logic. I
was mostly interested in scavenging ICs from the thing, so I never
figured out what the PCBs belonged to.
On the other hand, I have a couple of Eurobus wire-wrap boards outfitted
with lots of 10K series ECL. It appears to be a 12-bit CPU, complete
with memory and registers. The clock on it is 40MHz. I don't know
what it could have been. Mostly, I consider the boards to be a source
of gold-plated wire-wrap pins.
--Chuck
Personally, I preferred "the Naked
Mini"
Used for porn world wide.:)
--Chuck
9:50 p.m.
On 5/11/2019 9:28 PM, allison via cctalk wrote:
On 05/11/2019 09:30 PM, ben via cctalk wrote:
No BUT's
I have my cpu designed for 1976, with NO pipeline and a 6900 memory
cycle @ .75 us. I suspect about half the speed and half the price
had it been built in that era compared to a pdp 11.
On 5/11/2019 6:28 PM, allison via cctalk wrote:
TTl in general is slow a ALU based on 181 is hitting the wall at 5mhz
with 12 or 32 but carry lookahead.
Not all were 74181 based, Thats an early 1972
part and but 1975 it was
already getting old though useful as it evolved to 74S and 74F series.
The 82s100 and 105 series were out there and even by 1980 the AMD 2900C
series was getting long in the tooth. Mask programable gate arrays were
in the 1000 and up gate level by 1980 and growing by doubles every 6
months to a year. Don't got get programmables like PAL/GAL logic.
There was a lot of designs and even inside DEC you might see several
approaches depending on what machine and the specific date.? For example
the 780, 750 and 730 used very different technology.? I will not go into
those that also went the ECL {10K, 100K, 1M families] route.
74181 is FAST, but I disagree with the way most computer architecture is designed. You
have a fast micro code cycle, that is out of sync with
main memory, that tries to emulate a Harvard? Memory model.
It looks fast only on paper or demo programs sadly.
The few schematics I have seen (PDP 8/11) have 74H logic hidden
inside so you can't say they are pure TTL logic.
Yes, they are mostly TTL and the typical 8efm use MSI ttl such as
7481, a bunch of them.
I'm likely one of the few that took a 8E and ran semiconductor ram then
pushed the clock up to the breaking point and you get to about 4x and
you start getting timing errors and critical path delays that mess with
the logic. However at 4X you doing a lot and decently fast but you
needs a faster generation of logic.
>
> ?A cpu instruction has 4 parts in general
> ?a) getting the instruction and literal data from memory
> ?b) calculating the the effective address
> ?c) fetching the data from memory? c) ouputing data
> ?d) using the data d) saving to memory.
> Many of those things can be done in parallel.
Or
pipe lining, I don't mind tricks being used to
speed up a system,but knowing how slow a instruction
is, or what side effects can be very important.
The name for that is system overhead and PDP-8 had
little and what it
did have was written in assembler for speed and compact code as it was
also space constrained.
I don't know, I suspect 3-4 users would bog down a 8 time sharing.
mind you time sharing meant back then meant 4 people editing files
not like to day, where 3 or 4 windows are running with 30 back ground tasks.
It was a marvel how the machines worked with so little core.
Allison, have the shirt.
I have the paper tape.
:)
Ben.
5:32 p.m.
I'm building my own 8-bit CPU from TTL chips, and
this caused me to
think: how were 32-bit minis built in the late 70s and early 80s? In
particular, how was the ALU built? I know about the 74181 4-bit ALU,
and I know (from reading A Soul of a New Machine) that PALs were also
used.
I'd be curious to know how many designs used the 74181 instead of
scratch logic in the early 70s. I doubt many custom chips were done
until mid-late 80s.
Prime used 74181 chips for some of their CPUs. I have a 150 CPU board
(1980, though it was likely a relatively minor rehash of an older
board), for example.
Prime and Data General both used AMD2901 (1975) family stuff in some of
their designs.
Prime definitely had a lot of the logic into VLSI chips on their CPU
boards in the late 80s time frame. By the end (early 90s), a CPU board
was one or two big CMOS chips and a lot of empty space.
De
13 May
13 May
8:59 a.m.
Prime used 74181 chips for some of their CPUs. I have
a 150 CPU
board (1980, though it was likely a relatively minor rehash of an
older board), for example.
To extend this comment, I found 74S181 chips in the schematics for
Prime's first machines, the P100/P200/P300, with dates of 1972-73.
De
11 May
11 May
5:47 p.m.
On 5/11/2019 5:14 PM, Warren Toomey via cctalk wrote:
I'm building my own 8-bit CPU from TTL chips, and
this caused me to think:
how were 32-bit minis built in the late 70s and early 80s? In particular,
how was the ALU built? I know about the 74181 4-bit ALU, and I know (from
reading A Soul of a New Machine) that PALs were also used.
Did companies get custom chips fabricated, or was it all off-the-shelf chips
with a few PALs sprinkled in?
Thanks, Warren
8 bit computers are EVIL. REPENT DEAR BROTHER.
I WILL PRAY FOR YOU.
24 bit computers are HOLY AND DIVINE.
Building a 12/24 BIT CPU with 8 bit I/O.
(back on topic)
Early 70's computers other than IBM used TTL, and fast
core memory with mostly a 16 bit word width. Other than
the PDP 11, most computers where adapted from the transistor
era with tweaks added for banks of memory.When the late 70's
came around commercial customers had a large main frame computer
or small control computer from a few years earlier with FAST
TTL (S)logic, PDP 11's, IBM 360's or clones,or TTL standard/H like
PDP 8 or NOVA computer.
Bit slice logic like the 2901 alu, (1975) would make for
nice low cost 16/32 bit cpu with byte load/store.
The market for 32 bit computers was decided however
to sell FAST LARGE systems (floating point/64K+ memory)
like the VAX (S TTL) or upgrade other designs like the NOVA computer with
Custom or semi-custom (PAL logic) logic.
INTEL being slow with the forgotten APX 432 design
came out with 8086 leaving us with the defective CPU's
of today.
Ben's view point.
I am doing my computer with a FPGA development system
for design logic and testing and later using 2901's
and LS TTL with 3 proms used for the alu/control cards.
I have A nice 8/16/32 cpu design with 512KB of memory
(2901 alu )but I can't get it to route correctly. The 12/24 bit
cpu just fits with the FREE develpment software.
For a few K $ I can get the better version with being able
route by hand my logic to meet timing specs.
Once hardware SD card/serial port and software are working
I then will port the design to TTL.
I may need to write my own tiny langage to boot strap
my system.
Ben.
PS:
16 bit computer format
[op 3..1][ac 3..1][mode 3..1][ix 3..1][aux][k 3..1]
The tricky part is K is the upper 3 address bits
to extend 16 bit offset to 19 bits or a auto indexing
mode. This would be valid memory for the late 70's
early 1980's but not for today.
12 May
12 May
12:06 a.m.
-----Original Message-----
From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of ben via cctalk
Sent: 12 May 2019 01:48
To: cctalk at classiccmp.org
Subject: Re: How were 32-bit minis built in the 70s/80?
On 5/11/2019 5:14 PM, Warren Toomey via cctalk wrote:
They certainly thought that at Jodrell Bank, an outpost of the University of Manchester
http://www.jodrellbank.net/
in 1964 they started using Ferranti Argus 100 computers to control the radio telescopes.
http://www.computinghistory.org.uk/det/32443/Ferranti-Argus-100/
these were programmed in FORTH and the 24 bit word was ideal for storing astronomical
co-ordinates as sixed packed decimal digits.
So much so that when Ferranti stopped making the Argus 100 they created bit-slice
emulations of the machine using AMD2900 chips
I'm building my own 8-bit CPU from TTL chips,
and this caused me to think:
how were 32-bit minis built in the late 70s and early 80s? In
particular, how was the ALU built? I know about the 74181 4-bit ALU,
and I know (from reading A Soul of a New Machine) that PALs were also
used.
Did companies get custom chips fabricated, or was it all off-the-shelf
chips with a few PALs sprinkled in?
Thanks, Warren
8 bit computers are EVIL. REPENT DEAR BROTHER.
I WILL PRAY FOR YOU.
24 bit computers are HOLY AND DIVINE.
Building a 12/24 BIT CPU with 8 bit I/O.
(back on topic)
Early 70's computers other than IBM used TTL, and
fast core memory with
mostly a 16 bit word width. Other than the PDP 11, most computers where
adapted from the transistor era with tweaks added for banks of
memory.When the late 70's came around commercial customers had a large
main frame computer or small control computer from a few years earlier with
FAST TTL (S)logic, PDP 11's, IBM 360's or clones,or TTL standard/H like PDP 8
or NOVA computer.
Bit slice logic like the 2901 alu, (1975) would make for nice low cost 16/32 bit
cpu with byte load/store.
The market for 32 bit computers was decided however to sell FAST LARGE
systems (floating point/64K+ memory) like the VAX (S TTL) or upgrade other
designs like the NOVA computer with Custom or semi-custom (PAL logic)
logic.
INTEL being slow with the forgotten APX 432 design came out with 8086
leaving us with the defective CPU's of today.
The AMD2900 could be used to build 24 bit CPUs as well....
Ben's view point.
I am doing my computer with a FPGA development system for design logic
and testing and later using 2901's and LS TTL with 3 proms used for the
alu/control cards.
I have A nice 8/16/32 cpu design with 512KB of memory
(2901 alu )but I can't get it to route correctly. The 12/24 bit cpu just fits with
the FREE develpment software.
For a few K $ I can get the better version with being able route by hand my
logic to meet timing specs.
Once hardware SD card/serial port and software are working I then will port
the design to TTL.
I may need to write my own tiny langage to boot strap my system.
Ben.
Best of luck
Dave
PS:
16 bit computer format
[op 3..1][ac 3..1][mode 3..1][ix 3..1][aux][k 3..1] The tricky part is K is the
upper 3 address bits to extend 16 bit offset to 19 bits or a auto indexing
mode. This would be valid memory for the late 70's early 1980's but not for
today.
11 May
11 May
5:50 p.m.
Warren said
I'm building my own 8-bit CPU from TTL chips, and
this caused me to think:
how were 32-bit minis built in the late 70s and early 80s? In particular,
how was the ALU built? I know about the 74181 4-bit ALU, and I know (from
reading A Soul of a New Machine) that PALs were also used.
Did companies get custom chips fabricated, or was it all off-the-shelf chips
with a few PALs sprinkled in?
Thanks, Warren
I could be remembering incorrectly but I think the Gould PN6080 mini we had exclusively
for third year
comp sci at Macquarie Uni in the mid/late 80s was 32-bit made up of AMD2900 family logic
(2901 ALU's).
I can't verify that now as it's hard to find anything much at all about the Gould
mini's on the web (they
advertised them as superminis back then) but our machine running UTX/32 was pretty easy to
bring to a
complete crawl with students all trying to get their Prolog assignments running before
deadlines.
The lecturer didn't like us using 'cut' so the stack used to grow enormous and
things would go downhill
from there. That, and the two disks - one good one that
had the system and staff accounts filesystem and
the other chronically dodgy one
that held the student accounts and temp - is about all I remember of it.
Steve
7:17 p.m.
On Sat, May 11, 2019 at 8:50 PM Steve Malikoff via cctalk <
cctalk at classiccmp.org> wrote:
I could be remembering incorrectly but I think the
Gould PN6080 mini we
had exclusively for third year
comp sci at Macquarie Uni in the mid/late 80s was 32-bit made up of
AMD2900 family logic (2901 ALU's).
Purdue EE had I think 2 Gould PowerNode 9080s. I don't know anything about
the internals, but Purdue EE was doing development or testing for them. It
might have been a port of 4.3 BSD. As an undergraduate you could get an
account on en.ecn.purdue.edu for the asking and it was significantly faster
than the overloaded Dual VAXen. It also crashed from time to time.
-chuck
12 May
12 May
8:34 a.m.
On Sat, May 11, 2019 at 10:17 PM Charles Dickman via cctalk <
cctalk at classiccmp.org> wrote:
On Sat, May 11, 2019 at 8:50 PM Steve Malikoff via
cctalk <
cctalk at classiccmp.org> wrote:
The SEL (later Gould, later Encore) line was designated in two ways
27/nn, 57/nn, 87/nn for their machines which ran their real time OS, MPX
30nn, 60nn, 90nn for their machines which ran their Unix variant, UTX.
IIRC, the nn was 20, 50, or 80. Larger numbers designating increasing
capacity.
The 3000, 6000, 9000 series were virtually identical to the real time
versions.
They just upped the first digit and took out the "/".
All were true 32 bit. ISTR you could update a 20 to a 50 with a board swap,
since the backplane bus was the same. The 80s were dual cabinet machines,
more boards for the CPU and more space for memory.
The 87/9000 series were ECL based. I can't remember what technology
was in the 2x and 5x series.
I could be remembering incorrectly but I think
the Gould PN6080 mini we
had exclusively for third year
comp sci at Macquarie Uni in the mid/late 80s was 32-bit made up of
AMD2900 family logic (2901 ALU's).
Purdue EE had I think 2 Gould PowerNode 9080s. I don't know anything about
the internals, but Purdue EE was doing development or testing for them. It
might have been a port of 4.3 BSD. As an undergraduate you could get an
account on en.ecn.purdue.edu for the asking and it was significantly
faster
than the overloaded Dual VAXen. It also crashed from time to time.
Perdue also had Gorge Goble. https://en.wikipedia.org/wiki/George_H._Goble,
who was a character.
-chuck
9:11 a.m.
On 05/12/2019 10:34 AM, Tony Aiuto via cctalk wrote:
Perdue also had Gorge Goble. https://en.wikipedia.org/wiki/George_H._Goble,
who was a character.
INDEED! I sold him a scrap refrigeration compressor which
he used to prove that his proprietary mix of refrigerants
would return the oil to the compressor over a variety of
conditions.
He developed several replacements for the banned R-12, and
got patents on them. But, I don't think he ever made any
money with that, the HUGE chemical giants saw to that.
Jon
8:34 p.m.
On Sun, May 12, 2019, 11:35 Tony Aiuto via cctalk <cctalk at classiccmp.org wrote:
Perdue also had Gorge Goble. https://en.wikipedia.org/wiki/George_H._Goble
,
who was a character.
ghg still works at Purdue in the same department (Engineering Computer
Network).
Perdue on the other hand sells you chicken at the grocery store.
Pat
12:16 a.m.
-----Original Message-----
From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of Steve Malikoff
via cctalk
Sent: 12 May 2019 01:50
To: General Discussion: On-Topic and Off-Topic Posts
<cctalk at classiccmp.org>
Subject: Re: How were 32-bit minis built in the 70s/80?
Warren said
Also in the UK GEC used AMD2900 IC's for some of the GEC4000 series. Some details
here:-
https://en.wikipedia.org/wiki/GEC_4000_series
we used them in NERC (Natural Environment Research Council, www.nerc.ac.uk) as both X.25
packet switches and as general purpose computers in which role they were universally hated
as the Fortran compiler was ANSI compliant in the draconian sense of the word and the
scientists were used to DIGITAL Fortran which had many extensions.
Some history of the JANET network here:-
https://www.jisc.ac.uk/sites/default/files/janet-news-24-pull-out-april-201…
Dave
I'm building my own 8-bit CPU from TTL chips,
and this caused me to think:
how were 32-bit minis built in the late 70s and early 80s? In
particular, how was the ALU built? I know about the 74181 4-bit ALU,
and I know (from reading A Soul of a New Machine) that PALs were also
used.
Did companies get custom chips fabricated, or was it all off-the-shelf
chips with a few PALs sprinkled in?
Thanks, Warren
11 May
11 May
6:40 p.m.
On 5/11/19 4:14 PM, Warren Toomey via cctalk wrote:
I'm building my own 8-bit CPU from TTL chips, and
this caused me to think:
how were 32-bit minis built in the late 70s and early 80s? In particular,
how was the ALU built? I know about the 74181 4-bit ALU, and I know (from
reading A Soul of a New Machine) that PALs were also used.
What logic family? There were some minis built with ECL for example.
--Chuck
8:26 p.m.
On 05/11/2019 06:14 PM, Warren Toomey via cctalk wrote:
I'm building my own 8-bit CPU from TTL chips, and
this caused me to think:
how were 32-bit minis built in the late 70s and early 80s? In particular,
how was the ALU built? I know about the 74181 4-bit ALU, and I know (from
reading A Soul of a New Machine) that PALs were also used.
Did companies get custom chips fabricated, or was it all off-the-shelf chips
with a few PALs sprinkled in?
There were also the AMD2901, 2903, 29203 family of bit-slice
components, with the 2910 sequencer. I built a 32-bit basic
microengine in about 1982, but the software development
effort eventually led me to stop work on it. I was planning
to implement the IBM 360 instruction set, with extensions,
as it was very easy to implement with microcode.
See http://pico-systems.com/stories/1982.html for some
description and photos.
Apollo built some machines which I think were programmed at
the microinstruction level, without microcode, using 2903's,
I think.
The VAX 11/780 used 74S181 ALU chips, I think. There were
not all that many 32-bit minis.
I can think of Interdata 7/32 and 8/32 models that were
32-bit. SEL also made a 32-bit mini.
The VAX 11/780 was completely done with off-the-shelf ICs.
Later VAXes went to semi-custom ICs, and the MicroVAX line
used full-custom ICs. I suspect many other makers were so
small, they could only use off the shelf parts.
Jon
13 May
13 May
6:20 a.m.
On May 11, 2019, at 11:26 PM, Jon Elson via cctalk
<cctalk at classiccmp.org> wrote:
On 05/11/2019 06:14 PM, Warren Toomey via cctalk wrote:
The VAX 730 was built with 2901s.
DEC used 2901s in other places too; the UDA50 was built that way (2901 with 2910
sequencer). They had a custom assembler with two opcodes per line, one for the ALU and
one for the sequencer. The condition codes were those from the preceding instruction, not
the current ALU instruction, so you could see oddball stuff like this:
clr r0; bne foo
A bit like branch delay slot programming in MIPS...
On the subject of custom chips: DEC used gate arrays a lot. For example there is the Pro
380 in which much of the discrete chip logic from the Pro 350 has been absorbed into one
or two gate arrays, with all the unnecessary flexibility of the original chips omitted.
Those were CMOS I believe.
The Western Research Lab (in Palo Alto, down the road from Stanford) had a project
somewhat later to build VLSI full-custom designs in ECL. They built a whole set of design
tools that were very clever, allowing mixing of description anywhere from geometry to
C-like programs. And the actual layout generation was rule-based so they could switch to
a different factory that used different design rules with pretty much just a recompilation
of the design. They needed that; there were a number of ECL fabs at the time but they
were all shutting down. They designed a 1 GHz Alpha, and/or MIPS, and built a number of
test chips but I don't know that a complete CPU was ever made. They also did early
work on how to power and cool high powered chips; those designs ran over 100 watts which
at the time was utterly unheard of.
There are some internal tech reports documenting this work; I don't know that any of
it was ever published outside.
paul
I'm building my own 8-bit CPU from TTL chips,
and this caused me to think:
how were 32-bit minis built in the late 70s and early 80s? In particular,
how was the ALU built? I know about the 74181 4-bit ALU, and I know (from
reading A Soul of a New Machine) that PALs were also used.
Did companies get custom chips fabricated, or was it all off-the-shelf chips
with a few PALs sprinkled in?
There were also the AMD2901, 2903, 29203 family of bit-slice components, with the
2910 sequencer. 
8:31 a.m.
On Mon, May 13, 2019 at 8:20 AM Paul Koning via cctalk
<cctalk at classiccmp.org> wrote:
Yep. I pulled some 2901s from a VAX 11/730 CPU board in the early 90s
to repair a Tempest "Math Box" (we were doing our own repairs on our
VAXen in the late 80s/early 90s, and we had a stack of dead and
questionable boards in our engineering area, so one gave its life to
repair an arcade machine).
There were
also the AMD2901, 2903, 29203 family of bit-slice components, with the 2910 sequencer.
The VAX 730 was built with 2901s. On the subject of custom chips: DEC used gate arrays
a lot. For example there is the Pro 380 in which much of the discrete chip logic from the
Pro 350 has been absorbed into one or two gate arrays, with all the unnecessary
flexibility of the original chips omitted.
What sort of flexibility was omitted? I have both models and the
board layout difference is obvious (there's so much room on the Pro380
that it has a huge RAM field right on the mainboard instead of on two
daughter cards (plus any on the CTI bus).
-ethan
9:35 a.m.
On May 13, 2019, at 11:31 AM, Ethan Dicks
<ethan.dicks at gmail.com> wrote:
On Mon, May 13, 2019 at 8:20 AM Paul Koning via cctalk
<cctalk at classiccmp.org> wrote:
...
The 350 uses Intel chips for various functions, for example an interrupt controller chip
(from the original PC, I think?) that has a bunch of mode choices. Some of them are
typical Intel bad ideas, like edge triggered interrupts. Also, vectors are programmable.
In the DEC software one choice was used and the others were not needed; for example,
interrupts are level triggered because that's the only right way to do it. So in the
380, the gate array implements an interrupt controller that's like the used settings
of the 350 chips, but omitting all the other modes that aren't used.
As a result, emulating a 380 is quite a lot easier than emulating a 350, unless you make
it a "380 style subset of the 350".
paul
On the subject of custom chips: DEC used gate
arrays a lot. For example there is the Pro 380 in which much of the discrete chip logic
from the Pro 350 has been absorbed into one or two gate arrays, with all the unnecessary
flexibility of the original chips omitted.
What sort of flexibility was omitted? I have both models and the
board layout difference is obvious (there's so much room on the Pro380
that it has a huge RAM field right on the mainboard instead of on two
daughter cards (plus any on the CTI bus).
2050
days inactive
2052
days old
23 comments
14 participants
participants (14)
-
allisonportable＠gmail.com -
bfranchuk＠jetnet.ab.ca -
cclist＠sydex.com -
chd＠chdickman.com -
dave.g4ugm＠gmail.com -
drb＠msu.edu -
elson＠pico-systems.com -
ethan.dicks＠gmail.com -
nw＠retrocomputingtasmania.com -
pat＠vax11.net -
paulkoning＠comcast.net -
steven＠malikoff.com -
tony.aiuto＠gmail.com -
wkt＠tuhs.org