RTL Logic - test-drb@ccmp.vtda.org

7 Jan 2005

I did wired-and with open collector TTL gates all the time... common as dirt! LOL

-----Original Message-----
From: Tom Jennings &lt;tomj(a)wps.com&gt;
Sent: Jan 7, 2005 3:59 PM
To: Steve Thatcher &lt;melamy(a)earthlink.net&gt;et>, 
	"General Discussion: On-Topic and Off-Topic Posts"
&lt;cctalk(a)classiccmp.org&gt;
Subject: RE: RTL Logic

On Fri, 7 Jan 2005, Steve Thatcher wrote:

...
  dirt has been known to be found in most places in the
world...

 doing a wired-or and wired-and depends on reading IC specifications for specific chips.
It is what design engineers do... 
Sorry for being so obtuse! Phrase meant: "wire OR/etc was very
common in RTL".

I tried wired-OR once in TTL, didn't like the results :-)

...

 -----Original Message-----
 From: Tom Jennings &lt;tomj(a)wps.com&gt;

 It varies from chip to chip and family to family. Wire OR/etc was
 common as dirt.