Wow. Impressive reverse engineering work. Congrats! Marc

On Wed, May 30, 2018 at 7:09 PM, Marc Howard via cctalk <cctalk at classiccmp.org> wrote: The older analyzers were never that great for serial protocol decoding. The solution used with the HP 10342B RS-232 preprocessor interface was to throw hardware at the problem with a Zilog SIO/1 to turn the serial bits into parallel bytes, along with a Z80 CPU to configure the SIO/1. http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/pho… The 16700 series software has the B4601B Serial Analysis Tool Set. You need to install a license to use that, which has been made available. I have never really tried to do anything with the B4601B Serial Analysis Tool Set and have no idea if it would be of any help for I2C analysis.

Wow. That is cheap. Anyone ever use it? What are its limitations in real world situations? ________________________________________ From: cctalk <cctalk-bounces at classiccmp.org> on behalf of Al Kossow via cctalk <cctalk at classiccmp.org> Sent: Friday, June 1, 2018 11:09 AM To: cctalk at classiccmp.org Subject: Re: Logic Analyzer software for the HP-IB/RS-232 bus pre-processor HP 10342B On 5/30/18 7:09 PM, Marc Howard via cctalk wrote: Today it may be easier just to get one of the inexpensive 16 channel USB analyzers with built-in i2c decoding like a DSLogic http://www.dreamsourcelab.com/order.html

On Wed, May 30, 2018 at 7:07 PM, Curious Marc <curiousmarc3 at gmail.com> wrote: It wouldn't have been possible for me to do this without source code provided in the 16900-series logic analyzer Analysis AddIn Tool. The agIalEngine.cpp source file provided there contains a complete IAL style inverse assembler .R file parser into the variable and constant segment, the instruction opcode segment, and the string segment, plus an interpreter to execute the instruction opcodes. So it was mostly trying to figure out exactly what the agIalEngine.cpp source code does and writing something a similar tool that could execute in a standalone environment, and output text representations of everything in the .R file instead of interpreting and executing it. I hope I can do something similar to figure out the IA file format used by the 1630 series, just for completeness, and maybe be able to write an equivalent to the IALDOWN tools for the 1630 series. It appears that the 1630 series IA files start with the same .R files, then flatten them down to the three segments, then add some header information. But they also break the resulting file in a block structure with a 16-bit checksum on each block using an unknown algorithm. My current plan is to try hooking another logic analyzer up to a 1630 to observe what the 6809 CPU is doing when it computes checksums. I tried using CRC RevEng without any luck. Could be user error and I don't know how to use that tool.