11 Dec
2008
11 Dec
'08
12:25 p.m.
All this talk of CPUs got me back onto thoughts of homebrew CPU design, which
has been a stalled project of mine for the last year or so.
So, has anyone come across a good online resource which compares vintage CPU
instruction sets? It'd be useful to see what 'core' instructions* were most
common back in the day and use that as a basis for my own homebrew effort; I
think I can probably rustle up things like hardware multiply and divide, but
really don't want an all-singing solution. KISS and all that. :-)
* My hands-on knowledge is pretty much limited to Z80, 6502, 68000 and x86,
and it'd be nice to go a little further back in time - but hopefully without
having to download and digest many different databooks!
cheers
Jules
11 Dec
11 Dec
2:48 p.m.
Jules Richardson wrote:
All this talk of CPUs got me back onto thoughts of homebrew CPU
design, which has been a stalled project of mine for the last year or so.
Check here for ideas.
http://members.iinet.net.au/~daveb/simplex/simplex.html
So, has anyone come across a good online resource
which compares
vintage CPU instruction sets? It'd be useful to see what 'core'
instructions* were most common back in the day and use that as a basis
for my own homebrew effort; I think I can probably rustle up things
like hardware multiply and divide, but really don't want an
all-singing solution. KISS and all that. :-)
* My hands-on knowledge is pretty much limited to Z80, 6502, 68000 and
x86, and it'd be nice to go a little further back in time - but
hopefully without having to download and digest many different databooks!
cheers
Jules
12 Dec
12 Dec
7 a.m.
bfranchuk at jetnet.ab.ca wrote:
Jules Richardson wrote:
Interesting! I've always been thinking of doing a bit-serial ALU, just to keep
parts down a little (speed isn't exactly an issue anyway! :-)
I actually got as far as cooking up a suitable design, but that's sadly in a
notebook that's in storage right now (although I think I can remember enough
to reproduce it). I've got no TTL handy here though right now (that's in
storage too), but was screwing around with writing a logic simulator the other
day, which will at least allow me to prototype some stuff.
cheers
Jules
All this talk of CPUs got me back onto thoughts of homebrew CPU
design, which has been a stalled project of mine for the last year or so.
Check here for ideas.
http://members.iinet.net.au/~daveb/simplex/simplex.html 
2:15 a.m.
>>>
So, has anyone come across a good
online resource which compares vintage CPU
instruction sets? It'd be useful to see what 'core' instructions* were most
common back in the day and use that as a basis for my own homebrew
effort;...
* My hands-on knowledge is pretty much limited to Z80, 6502, 68000 and x86,
and it'd be nice to go a little further back in time - but hopefully without
having to download and digest many different databooks!
<<<<
It sounds like what you really require is information on vintage computer
_architectures_ (probably from the programmers view).
The classic text on the subject is, luckily, available online from a rather
unexpected address:
http://research.microsoft.com/en-us/um/people/gbell/Computer_Structures__Rea
dings_and_Examples/contents.html
[Computer Structures: Readings & Examples, by Gordon Bell]
As personal thoughts on the subject and going backwards in time I'd think of
looking-at and comparing the following.
The two pre-micro classics, nay extremes, of CISC:
*IBM system 360/370/... [Multi-GP-register - store organisation with a
sprinkling of store-store operarions]
*DEC VAX (and its simpler predecessor, the PDP-11) [address-modes-R-us]
The RISC before there ws RISC:
*CDC6600
The classic 36-bit architectures
*IBM709/7090/7094 [single accumulator/few index registers]
*GE6xx/Multics/Honeywell L66 [similar architecture, taken to its limits, and
(in later models) even more address modes than a VAX]
Traditional mini-computer
*PDP-8
*PDP-11
any of hundreds of 16 or 18 bit accumulator-store designs ... they tend to
be very similar - like PDP9 or CDC1700 or EAL640 or ...
"Weirdos"
*Burroughs B5500 [stack structured]
*IBM 1620 [pure store-store organisation]
*IBM 650 [and the effect of having program memory on a drum]
Other cases of interest
*Ferranti Atlas [virtual memory before IBM invented tomorrow]
*FP6000 became ICT1900 [multi-register - store but simpler and less general
than the '360 ... and 24 bits]
*MU5/ICL2900 [designed for block-structured high-level-languagues - pity
ICL's main market was
for people who used COBOL]
Andy
15 Dec
15 Dec
2:26 p.m.
From: Andy Holt
Sent: Friday, December 12, 2008 2:15 AM
[snip ]
[Computer Structures: Readings & Examples, by
Gordon Bell]
As personal thoughts on the subject and going
backwards in time I'd think of
looking-at and comparing the following.
The two pre-micro classics, nay extremes, of CISC:
*IBM system 360/370/... [Multi-GP-register - store
organisation with a
sprinkling of store-store operarions]
*DEC VAX (and its simpler predecessor, the PDP-11) [address-modes-R-us]
The RISC before there ws RISC:
*CDC6600
The PDP-10 is often described this way.
The classic 36-bit architectures
*IBM709/7090/7094 [single accumulator/few index
registers]
*GE6xx/Multics/Honeywell L66 [similar architecture, taken to its limits, and
(in later models) even more address modes than a VAX]
...and I'm surprised that you don't consider the PDP-10 to be a classic 36-bit
architecture. Or the SDS Sigma series, for that matter.
[snip]
Rich Alderson
Server Engineer, PDPplanet Project
Vulcan, Inc.
505 5th Avenue S, Suite 900
Seattle, WA 98104
mailto:RichA at vulcan.com
(206) 342-2239
(206) 465-2916 cell
3:09 p.m.
From: Andy Holt
Sent: Friday, December 12, 2008 2:15 AM
The two pre-micro classics, nay extremes, of CISC:
*IBM system 360/370/... [Multi-GP-register - store
organisation with a
sprinkling of store-store operarions]
I missed this observation the first time. You've obvioiusly never
run into a CDC STAR-100. 48 bit virtual addressing (bit addressed),
256 64-bit registers with an instruction set that, while it allocated
8 bits to the opcode, used a second 8-bit field (the "G" bits) in
many instructions yielding thousands of variations (that included
strings (including BCD arithmetic) and vectors (including sparse and
compressed). If you ever hankered after a "polynomial evaluation" or
byte-string modulo addition (with variable modulus) instruction, the
STAR had it for you.
Postively and grotesquely baroque in in the range of instructions.
The hardware reference manual is on bitsavers; most of the almost 19
megabyte text is instruction descriptions. The one for "Search
Masked Key Byte" occupies 3 pages alone.
The "kitchen sink" of supercomputers.
Cheers,
Chuck
6:03 p.m.
Rich Alderson wrote:
[snip]
I would consider the Sigma 5/6/7/9 series RISC for the day. Basic
load/store, multiple register sets. It
did have a few string instructions (move byte string, compare byte
string,edit byte string) but in general load/store.
Since the design was async most instructions completed in 1 clock
"cycle". The 5/6/7/9 were 32 bit.
The 16 bit Sigma 2/3 series had a nice small instruction set that I once
considered implementing in a
CPLD or FPGA. Just never had the time.
*IBM system 360/370/... [Multi-GP-register -
store organisation with a
sprinkling of store-store operarions]
*DEC VAX (and its simpler predecessor, the PDP-11) [address-modes-R-us]
The RISC before there ws RISC:
*CDC6600
The PDP-10 is often described this way.
The classic 36-bit architectures
*IBM709/7090/7094 [single accumulator/few index
registers]
*GE6xx/Multics/Honeywell L66 [similar architecture, taken to its limits, and
(in later models) even more address modes than a VAX]
...and I'm surprised that you don't consider the PDP-10 to be a classic 36-bit
architecture. Or the SDS Sigma series, for that matter.
[snip]
Rich Alderson
Server Engineer, PDPplanet Project
Vulcan, Inc.
505 5th Avenue S, Suite 900
Seattle, WA 98104
mailto:RichA at vulcan.com
(206) 342-2239
(206) 465-2916 cell
--
Joe Chisolm
Computer Translations, Inc.
Marble Falls, Tx.
830-265-8018
16 Dec
16 Dec
9:26 a.m.
>>>> "Rich" == Rich Alderson
<RichA at vulcan.com> writes:
Rich> From: Andy Holt Sent: Friday, December 12, 2008 2:15 AM
> ...The RISC before there ws RISC:
> *CDC6600
Rich> The PDP-10 is often described this way.
Interesting. I wouldn't, for a couple of reasons. The PDP-10
instruction set is quite large. Also, RISC generally means load/store
instructions and the rest of the ops are register based. CDC 6000
series does that, as do contemporary RISC architectures like MIPS --
but the PDP-10 doesn't.
paul
1:32 p.m.
From: Paul Koning
Sent: Tuesday, December 16, 2008 9:26 AM
>>>> "Rich" == Rich Alderson
<RichA at vulcan.com> writes:
Rich>> From: Andy Holt Sent: Friday, December 12, 2008 2:15 AM
>> ...The RISC before there ws RISC:
>> *CDC6600
Rich>> The PDP-10 is often described this way.
Interesting. I wouldn't, for a couple of reasons.
The PDP-10
instruction set is quite large. Also, RISC generally means load/store
instructions and the rest of the ops are register based. CDC 6000
series does that, as do contemporary RISC architectures like MIPS --
but the PDP-10 doesn't.
I'm well aware of where the PDP-10 architecture fails that definition.
On the other hand, nearly 30 years of programming the PDP-10 architecture
tells me that very nearly all the work done by a PDP-10 program is done
with accumulator load/store and accumulator-to-accumulator or accumulator
+ immediate data operations.
And the size of an instruction set is not indicative of the RISCiness of
the architecture.
Rich Alderson
Server Engineer, PDPplanet Project
Vulcan, Inc.
505 5th Avenue S, Suite 900
Seattle, WA 98104
mailto:RichA at vulcan.com
(206) 342-2239
(206) 465-2916 cell
5851
days inactive
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days old
8 comments
7 participants
participants (7)
-
andyh＠andyh-rayleigh.freeserve.co.uk -
bfranchuk＠jetnet.ab.ca -
cclist＠sydex.com -
jchisolm＠computer.org -
jules.richardson99＠gmail.com -
Paul_Koning＠Dell.com -
RichA＠vulcan.com