20 Apr
1999
20 Apr
'99
11:08 a.m.
--- allisonp(a)world.std.com wrote:
Correct, but the pulse that indicates the core
switched is delayed in
time Hence the critical slice time.
Ah! The light goes on!
Core size affects this as does the select current.
That makes perfect sense.
Actually the nuts have an adaquate hysteresis to make
a demo core but it
would not work useably well.
Funny you should mention demo core. I have had in the back of my mind for
several years now a project: demonstrate memory storage by building a mini-
core mat on top of an FPGA socket and drive it via some kind of parallel-
port A-D/D-A interface. The purpose of the demo would be to stick the
core mat into a ZIF socket, program it, display the bits on the screen,
remove the mat from the socket, turn it around and show how the bits have
moved... not particularly practical, but a good visual demonstration of
the technology. A special bonus is that the demonstrator can prove that
core is non-volatile by letting the audience see the plane out of the socket
between phases of the demonstration.
I'm thinking of a 4x4 or a 5x5 mat; nothing larger than 8x8. The test jig
could be even 2x2 inside a larger FPGA socket. The external circuit would
have to be able to select the half-currents on the X and Y planes, then
send a pulse and then time the return, yes? I have a general knowledge
of the sense amps and inhibit drivers for several PDP-8 models. Is it
possible to simplify that circuit if you knew that you had read cycle time
of several or tens of milliseconds? Perhaps by having one circuit to control
all the X lines, one circuit to control all the Y lines and some sort of
analog multiplexer?
Ferrites used for beads have low permability. But
since they are available
I'd try one and see.
How do the different dimensions affect this all? (Most ferrite beads I've
seen are taller than their diameter (HoHo's, not KingDons, if you will).
In other words, the ferrite beads have a different aspect ratio compared
to the #2 nuts (or a standard ferrite core). How does this affect usability
as a memory device?
-ethan
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20 Apr
20 Apr
11:52 a.m.
Funny you should mention demo core. I have had in the
back of my mind for
several years now a project: demonstrate memory storage by building a mini-
core mat on top of an FPGA socket and drive it via some kind of parallel-
port A-D/D-A interface. The purpose of the demo would be to stick the
core mat into a ZIF socket, program it, display the bits on the screen,
remove the mat from the socket, turn it around and show how the bits have
moved... not particularly practical, but a good visual demonstration of
the technology. A special bonus is that the demonstrator can prove that
core is non-volatile by letting the audience see the plane out of the socket
Why a/d and d/a?
I'm thinking of a 4x4 or a 5x5 mat; nothing larger
than 8x8. The test jig
actually 8x8 by one bit is fairly easy to do.
of the sense amps and inhibit drivers for several
PDP-8 models. Is it
possible to simplify that circuit if you knew that you had read cycle time
of several or tens of milliseconds? Perhaps by having one circuit to control
all the X lines, one circuit to control all the Y lines and some sort of
analog multiplexer?
Foo, wrong way to go. Too top heavy. Also the cores even if slow switch
in the microsecond range.
How do the different dimensions affect this all?
(Most ferrite beads I've
seen are taller than their diameter (HoHo's, not KingDons, if you will).
In other words, the ferrite beads have a different aspect ratio compared
to the #2 nuts (or a standard ferrite core). How does this affect usability
as a memory device?
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allisonp＠world.std.com -
ethan_dicks＠yahoo.com