fpga pdp's - test-drb@ccmp.vtda.org

13 Jun 2009

Brad Parker <brad at heeltoe.com> wrote:

...
  Eric Smith wrote:
  > Brad Parker wrote:
> >> I did a "direct decode" pdp-11 in verilog recently just to see how

> >> big it would be (and because I was frustrated with the pop-11 
> >> project).  It fits nicely & boots RT11 at 50mhz.
 > At that speed, surely it hasn't finished booting RT11 yet!  sorry, I
don't get the joke.  clock is 50mhz, or 20ns; each state is one 
 clock and on average
 an instruction is 3 states.  I calculated 10mips.  it seems to boot much 
 faster than my 11/44  :-) 

 what did I miss? 
That case matters. :-)

m = milli
M = Mega

	Johnny

-- 
Johnny Billquist                  || "I'm on a bus
                                   ||  on a psychedelic trip
email: bqt at softjar.se             ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol