Don't you also need to "delayer" the chip to get all the hidden features? I thought the process of reconstructing the polygons required that each successive layer be exposed. From the "top" I'd think you'd only see a single metal layer. But then again, on a old chip like that there may only *be* one metal layer :-) My primitive understanding is that there will be a "base layer" with junctions and one or more metal layers on top doing the interconnect. (I try and steer clear of physical design, or "PD" as we call it, since it's seriously complex. but also interesting!) -brad

On Tue, Nov 10, 2015 at 1:39 PM, Brad Parker <brad at heeltoe.com> wrote: For late 1970s coarse geometry NMOS with only one metal layer, it's usually possible with only a single photomicrograph, especially if there isn't a thick passivation layer. That's how the 6502 was originally reverse-engineered. As the processes became more complex and added more metal layers, reverse-engineering has increasingly required delayering. The use of depletion mode nFETs for loads does make it a little more difficult, as you can't see the difference in the diffusion, but it's usually possible to infer which nFETs are the loads. The LSI-11, WD16, and WD9000 chipsets are three-supply-voltage NMOS, so they shouldn't even have any depletion loads to worry about. Depletion-load NMOS eliminated the +12V requirement, so was usually only used for single-supply 5V parts, Mostek pioneered depletion-load, and one of the earliest commercial uses was the Zilog Z80 CPU, which was originally fabbed by Mostek both under contract to Zilog and as Mostek's second-source. Usually along with depletion-load, an on-chip substrate bias generator eliminates the Vbb requirement, which was usually -5V.

On 11/10/15 3:47 PM, Brad Parker wrote: Variations of that ASIC are the core of HP's logic logic analyzers for a LONG time (at least while they were using 68K processors). One of my back burner projects has been to understand how they worked as an embedded system. Sadly, I've heard the person who designed it passed away this past year. One of the things that made HP magical in the 70's and 80's was how advanced their ASIC capabilites were compared to the competition.

fyi: from the 6502 faq: /* How do you turn bitmaps into polygons?/ We draw them in our custom Python app. We spent about two months looking at automatic vectorization and using the bitmaps to create polygon fragments, but neither of these was better than just sitting down and clicking out the polygons. It's almost essential to have our own vector drawing app, so we can control snapping, do fancy copy-paste, get good vector data, and greatly speed up the work. /* How did automatic vectorization fail?/ It was more work to clean up the results of automatic vectorization than to do clean work in the first place. Damage, dirt, and ambiguous or falsely detected features in the chip die shots create problems. We also rely on finding and modelingburied contacts <http://www.intel4004.com/buried.htm>like they would appear in the original fabrication masks, not like they appear in silicon. This is very difficult, if not impossible, to do automatically. I'm not surprised by this. So in the end, a human brain figured out where the polygons are. It might be a fun "internet distributed" project to farm out sections to lots of people and then assemble the results... -brad