< Do you mean if you execute a HALT instruction? If you do that, the Z80 < behaves as if it's continuously executing HALT instructions, performing < repeated bus cycles, including the RFSH signal part. No. Halt is a instruction. WAIT/ is a device pin. WAIT/ will hold cpu operation at the point where a read write or IO( read or write) operation takes place an freezes it until released. Most hardware front pannels used wait/ (or ready/) to stop the cpu. the WAIT/ state on z80 does not generate refresh as it's a extended T2 state and refresh is not output until the cpu proceds to the T3 state. so for those front pannels operatios were done this way: read an address; waiting that that address with data and address leds as the would be for bus contents. CPU is waiting in M1 state for z80 case (instruction read). Write data: Same as read case but the contents of the data switches are written to the current ram address. the write pulse is from the front pannel (cpu still waiting). RUN: remove wait/, operation procedes from where you are. STOP: Assert wait/ LOAD ADDRESS: JAM jump to address into cpu. the jump instuction is a buffer with it's imputs hard wired to C3h (JP in z80) and the address bytes that follow gated off the 16 front pannel switchs. Wait is re asserted to stop after the jump. LEDs will now contain the new address and data from the address in the switches. hardware front pannels are generally a lot of chips but no smarts. Allison