On Mar 2, 2018, at 5:37 AM, Noel Chiappa via cctalk
<cctalk at classiccmp.org> wrote:
From: Jerry Weiss
Typically execution of the RESET instruction in a user program is
treated as a NOP
Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of
the things that makes the PDP-11 impossible to virtualize; only HALT and SPL
trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT],
IIRC.
Re-affirming Noel's *most* from above: having been through a deep dive on the 11/45
during a restoration the last couple years, I know most of this material *is* explicit in
the 11/45 processor handbook, though maybe not in the obvious places.
Behavior of HALT, RESET, and SPL in all three modes is documented on page 13, in the
Processor Status Word section, for example. HALT and SPL behaviors are also noted on
their individual instruction pages, but the RESET behavior, strangely, is not.
WAIT is permitted in supervisor and user modes on the 11/45.
Current and previous mode bits in the PSW can be set but not cleared when in supervisor
and user modes on the 11/45. RTI/RTT/M[FT]P[DI] function uniformly, but given this PSW
behavior they can only effectively preserve or lower the processor mode, or access the
address space of same or lower modes, assuming the PSW is properly setup and handled by
kernel mode code. This is documented on page 24 of the processor handbook, in the
Multiprogramming section.
I don't recall explicit mention of the MMU reset behavior in the processor handbook,
but it may be squirreled away in there somewhere... I think I absorbed that bit of
critical info from the KT11-C maintenance manual when I was working through debugging the
one in my /45.
I am much less familiar with the documentation for later-model PDP-11s. It sounds like a
some of this info may have been "sanitized" from the later handbooks?
cheers!
--FritzM.