CPU design at the gate level - test-drb@ccmp.vtda.org

31 Oct 2001

The fake for that using discretes is one transistor per emitter used
with the bases and collectors as common.  The other is diodes.

The real problem is level shifting and the use of excess redundant
transistors.

Allison

-----Original Message-----
From: Greg Ewing &lt;greg(a)cosc.canterbury.ac.nz&gt;
To: classiccmp(a)classiccmp.org &lt;classiccmp(a)classiccmp.org&gt;
Date: Wednesday, October 31, 2001 8:04 PM
Subject: Re: CPU design at the gate level

...
 "Peter C. Wallace" &lt;pcw(a)mesanet.com&gt;om>:

> There was non-integrated RTL and DTL logic before ICs not sure about non
...
   integrated
TTL... 
I don't think non-integrated TTL is even possible using
standard parts. It relies on multiple-emitter transistors,
and I've never heard of anyone making those available
discretely.

Greg Ewing, Computer Science Dept, +--------------------------------------+
...
 University of Canterbury,    | A citizen of
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