TI 990 architecture - test-drb@ccmp.vtda.org

4 Oct 2007

Subject: Re: TI 990 architecture
From: Cameron Kaiser <spectre (at) floodgap.com>
Message-id: 200710021957.l92Jv8RK013898 (at) floodgap.com
Date: 2007-10-02 21:57:08

...
   If I remember
right, the architecure of the ti chip
 it used a pointer to ram as the internal registers. That would really
 bog down on byte wide bus. 
 But then chips like the 9995 do very well on a 8-bit data bus. IMHO the
 bigger problems with the 9900 implementation in the 99/4A were the external
 scratch pad (made internal for the 9995) and the presence of GROMs,
 requiring their own interpretation step and murderously slow serial access.

 Compare this to a system like the Tomy Tutor, which has a 9995 on an 8-bit
 bus too, but is significantly faster than the 99/4A despite being clocked
 slightly slower (10.7MHz os 
Rather than rely on sometimes parity afflicted memory I pulled down a spare 
board (TI99/4A black) and the TI system manuals and prints..

  10.738625mhz is the Video clock (TMS9918)
  12.000 is the CPU clock. (4phase 3MHz)

The print set indicates FOUR wait states (1.33uS) for every 8bit bus access
(to GROM, 9918 and Peripheral expansion). The 16bit bus has 128Words of
scratch ram and 4kWords of system rom(GPL interpreter) and no wait states. 
Since most of the active IO to memory space is to GROM or 9918 on the console
that speed cost overhead is both wait states and interpretive language.

The TI99/4 series is clearly not representative of TI9900 cpu performance.

However the idea of an interpretive system does reoccur in the computing world
(JAVA, UCSD PASCAL).

Allison